18c2ecf20Sopenharmony_ci* Microchip PIC32 SDHCI Controller 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThis file documents differences between the core properties in mmc.txt 48c2ecf20Sopenharmony_ciand the properties used by the sdhci-pic32 driver. 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ciRequired properties: 78c2ecf20Sopenharmony_ci- compatible: Should be "microchip,pic32mzda-sdhci" 88c2ecf20Sopenharmony_ci- interrupts: Should contain interrupt 98c2ecf20Sopenharmony_ci- clock-names: Should be "base_clk", "sys_clk". 108c2ecf20Sopenharmony_ci See: Documentation/devicetree/bindings/resource-names.txt 118c2ecf20Sopenharmony_ci- clocks: Phandle to the clock. 128c2ecf20Sopenharmony_ci See: Documentation/devicetree/bindings/clock/clock-bindings.txt 138c2ecf20Sopenharmony_ci- pinctrl-names: A pinctrl state names "default" must be defined. 148c2ecf20Sopenharmony_ci- pinctrl-0: Phandle referencing pin configuration of the SDHCI controller. 158c2ecf20Sopenharmony_ci See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ciExample: 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ci sdhci@1f8ec000 { 208c2ecf20Sopenharmony_ci compatible = "microchip,pic32mzda-sdhci"; 218c2ecf20Sopenharmony_ci reg = <0x1f8ec000 0x100>; 228c2ecf20Sopenharmony_ci interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; 238c2ecf20Sopenharmony_ci clocks = <&rootclk REF4CLK>, <&rootclk PB5CLK>; 248c2ecf20Sopenharmony_ci clock-names = "base_clk", "sys_clk"; 258c2ecf20Sopenharmony_ci bus-width = <4>; 268c2ecf20Sopenharmony_ci cap-sd-highspeed; 278c2ecf20Sopenharmony_ci pinctrl-names = "default"; 288c2ecf20Sopenharmony_ci pinctrl-0 = <&pinctrl_sdhc1>; 298c2ecf20Sopenharmony_ci }; 30