18c2ecf20Sopenharmony_ciSamsung Exynos SoC Low Power Audio Subsystem (LPASS)
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciRequired properties:
48c2ecf20Sopenharmony_ci
58c2ecf20Sopenharmony_ci - compatible		: "samsung,exynos5433-lpass"
68c2ecf20Sopenharmony_ci - reg			: should contain the LPASS top SFR region location
78c2ecf20Sopenharmony_ci			  and size
88c2ecf20Sopenharmony_ci - clock-names		: should contain following required clocks: "sfr0_ctrl"
98c2ecf20Sopenharmony_ci - clocks		: should contain clock specifiers of all clocks, which
108c2ecf20Sopenharmony_ci			  input names have been specified in clock-names
118c2ecf20Sopenharmony_ci			  property, in same order.
128c2ecf20Sopenharmony_ci - #address-cells	: should be 1
138c2ecf20Sopenharmony_ci - #size-cells		: should be 1
148c2ecf20Sopenharmony_ci - ranges		: must be present
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_ciEach IP block of the Low Power Audio Subsystem should be specified as
178c2ecf20Sopenharmony_cian optional sub-node. For "samsung,exynos5433-lpass" compatible this includes:
188c2ecf20Sopenharmony_ciUART, SLIMBUS, PCM, I2S, DMAC, Timers 0...4, VIC, WDT 0...1 devices.
198c2ecf20Sopenharmony_ci
208c2ecf20Sopenharmony_ciBindings of the sub-nodes are described in:
218c2ecf20Sopenharmony_ci  ../serial/samsung_uart.yaml
228c2ecf20Sopenharmony_ci  ../sound/samsung-i2s.txt
238c2ecf20Sopenharmony_ci  ../dma/arm-pl330.txt
248c2ecf20Sopenharmony_ci
258c2ecf20Sopenharmony_ci
268c2ecf20Sopenharmony_ciExample:
278c2ecf20Sopenharmony_ci
288c2ecf20Sopenharmony_ciaudio-subsystem {
298c2ecf20Sopenharmony_ci	compatible = "samsung,exynos5433-lpass";
308c2ecf20Sopenharmony_ci	reg = <0x11400000 0x100>, <0x11500000 0x08>;
318c2ecf20Sopenharmony_ci	clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
328c2ecf20Sopenharmony_ci	clock-names = "sfr0_ctrl";
338c2ecf20Sopenharmony_ci	#address-cells = <1>;
348c2ecf20Sopenharmony_ci	#size-cells = <1>;
358c2ecf20Sopenharmony_ci	ranges;
368c2ecf20Sopenharmony_ci
378c2ecf20Sopenharmony_ci	adma: adma@11420000 {
388c2ecf20Sopenharmony_ci		compatible = "arm,pl330", "arm,primecell";
398c2ecf20Sopenharmony_ci		reg = <0x11420000 0x1000>;
408c2ecf20Sopenharmony_ci		interrupts = <0 73 0>;
418c2ecf20Sopenharmony_ci		clocks = <&cmu_aud CLK_ACLK_DMAC>;
428c2ecf20Sopenharmony_ci		clock-names = "apb_pclk";
438c2ecf20Sopenharmony_ci		#dma-cells = <1>;
448c2ecf20Sopenharmony_ci		#dma-channels = <8>;
458c2ecf20Sopenharmony_ci		#dma-requests = <32>;
468c2ecf20Sopenharmony_ci	};
478c2ecf20Sopenharmony_ci
488c2ecf20Sopenharmony_ci	i2s0: i2s0@11440000 {
498c2ecf20Sopenharmony_ci		compatible = "samsung,exynos7-i2s";
508c2ecf20Sopenharmony_ci		reg = <0x11440000 0x100>;
518c2ecf20Sopenharmony_ci		dmas = <&adma 0 &adma 2>;
528c2ecf20Sopenharmony_ci		dma-names = "tx", "rx";
538c2ecf20Sopenharmony_ci		interrupts = <0 70 0>;
548c2ecf20Sopenharmony_ci		clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
558c2ecf20Sopenharmony_ci			 <&cmu_aud CLK_SCLK_AUD_I2S>,
568c2ecf20Sopenharmony_ci			 <&cmu_aud CLK_SCLK_I2S_BCLK>;
578c2ecf20Sopenharmony_ci		clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
588c2ecf20Sopenharmony_ci		pinctrl-names = "default";
598c2ecf20Sopenharmony_ci		pinctrl-0 = <&i2s0_bus>;
608c2ecf20Sopenharmony_ci	};
618c2ecf20Sopenharmony_ci
628c2ecf20Sopenharmony_ci	serial_3: serial@11460000 {
638c2ecf20Sopenharmony_ci		compatible = "samsung,exynos5433-uart";
648c2ecf20Sopenharmony_ci		reg = <0x11460000 0x100>;
658c2ecf20Sopenharmony_ci		interrupts = <0 67 0>;
668c2ecf20Sopenharmony_ci		clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
678c2ecf20Sopenharmony_ci			 <&cmu_aud CLK_SCLK_AUD_UART>;
688c2ecf20Sopenharmony_ci		clock-names = "uart", "clk_uart_baud0";
698c2ecf20Sopenharmony_ci		pinctrl-names = "default";
708c2ecf20Sopenharmony_ci		pinctrl-0 = <&uart_aud_bus>;
718c2ecf20Sopenharmony_ci	};
728c2ecf20Sopenharmony_ci };
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