18c2ecf20Sopenharmony_ci* ROHM BD9571MWV Power Management Integrated Circuit (PMIC) bindings 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciRequired properties: 48c2ecf20Sopenharmony_ci - compatible : Should be "rohm,bd9571mwv". 58c2ecf20Sopenharmony_ci - reg : I2C slave address. 68c2ecf20Sopenharmony_ci - interrupts : The interrupt line the device is connected to. 78c2ecf20Sopenharmony_ci - interrupt-controller : Marks the device node as an interrupt controller. 88c2ecf20Sopenharmony_ci - #interrupt-cells : The number of cells to describe an IRQ, should be 2. 98c2ecf20Sopenharmony_ci The first cell is the IRQ number. 108c2ecf20Sopenharmony_ci The second cell is the flags, encoded as trigger 118c2ecf20Sopenharmony_ci masks from ../interrupt-controller/interrupts.txt. 128c2ecf20Sopenharmony_ci - gpio-controller : Marks the device node as a GPIO Controller. 138c2ecf20Sopenharmony_ci - #gpio-cells : Should be two. The first cell is the pin number and 148c2ecf20Sopenharmony_ci the second cell is used to specify flags. 158c2ecf20Sopenharmony_ci See ../gpio/gpio.txt for more information. 168c2ecf20Sopenharmony_ci - regulators: : List of child nodes that specify the regulator 178c2ecf20Sopenharmony_ci initialization data. Child nodes must be named 188c2ecf20Sopenharmony_ci after their hardware counterparts: 198c2ecf20Sopenharmony_ci - vd09 208c2ecf20Sopenharmony_ci - vd18 218c2ecf20Sopenharmony_ci - vd25 228c2ecf20Sopenharmony_ci - vd33 238c2ecf20Sopenharmony_ci - dvfs 248c2ecf20Sopenharmony_ci Each child node is defined using the standard 258c2ecf20Sopenharmony_ci binding for regulators. 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ciOptional properties: 288c2ecf20Sopenharmony_ci - rohm,ddr-backup-power : Value to use for DDR-Backup Power (default 0). 298c2ecf20Sopenharmony_ci This is a bitmask that specifies which DDR power 308c2ecf20Sopenharmony_ci rails need to be kept powered when backup mode is 318c2ecf20Sopenharmony_ci entered, for system suspend: 328c2ecf20Sopenharmony_ci - bit 0: DDR0 338c2ecf20Sopenharmony_ci - bit 1: DDR1 348c2ecf20Sopenharmony_ci - bit 2: DDR0C 358c2ecf20Sopenharmony_ci - bit 3: DDR1C 368c2ecf20Sopenharmony_ci These bits match the KEEPON_DDR* bits in the 378c2ecf20Sopenharmony_ci documentation for the "BKUP Mode Cnt" register. 388c2ecf20Sopenharmony_ci - rohm,rstbmode-level: The RSTB signal is configured for level mode, to 398c2ecf20Sopenharmony_ci accommodate a toggle power switch (the RSTBMODE pin is 408c2ecf20Sopenharmony_ci strapped low). 418c2ecf20Sopenharmony_ci - rohm,rstbmode-pulse: The RSTB signal is configured for pulse mode, to 428c2ecf20Sopenharmony_ci accommodate a momentary power switch (the RSTBMODE pin 438c2ecf20Sopenharmony_ci is strapped high). 448c2ecf20Sopenharmony_ci The two properties above are mutually exclusive. 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ciExample: 478c2ecf20Sopenharmony_ci 488c2ecf20Sopenharmony_ci pmic: pmic@30 { 498c2ecf20Sopenharmony_ci compatible = "rohm,bd9571mwv"; 508c2ecf20Sopenharmony_ci reg = <0x30>; 518c2ecf20Sopenharmony_ci interrupt-parent = <&gpio2>; 528c2ecf20Sopenharmony_ci interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 538c2ecf20Sopenharmony_ci interrupt-controller; 548c2ecf20Sopenharmony_ci #interrupt-cells = <2>; 558c2ecf20Sopenharmony_ci gpio-controller; 568c2ecf20Sopenharmony_ci #gpio-cells = <2>; 578c2ecf20Sopenharmony_ci rohm,ddr-backup-power = <0xf>; 588c2ecf20Sopenharmony_ci rohm,rstbmode-pulse; 598c2ecf20Sopenharmony_ci 608c2ecf20Sopenharmony_ci regulators { 618c2ecf20Sopenharmony_ci dvfs: dvfs { 628c2ecf20Sopenharmony_ci regulator-name = "dvfs"; 638c2ecf20Sopenharmony_ci regulator-min-microvolt = <750000>; 648c2ecf20Sopenharmony_ci regulator-max-microvolt = <1030000>; 658c2ecf20Sopenharmony_ci regulator-boot-on; 668c2ecf20Sopenharmony_ci regulator-always-on; 678c2ecf20Sopenharmony_ci }; 688c2ecf20Sopenharmony_ci }; 698c2ecf20Sopenharmony_ci }; 70