18c2ecf20Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 28c2ecf20Sopenharmony_ci%YAML 1.2 38c2ecf20Sopenharmony_ci--- 48c2ecf20Sopenharmony_ci$id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml# 58c2ecf20Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_cititle: Calxeda DDR memory controller binding 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_cidescription: | 108c2ecf20Sopenharmony_ci The Calxeda DDR memory controller is initialised and programmed by the 118c2ecf20Sopenharmony_ci firmware, but an OS might want to read its registers for error reporting 128c2ecf20Sopenharmony_ci purposes and to learn about the DRAM topology. 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_cimaintainers: 158c2ecf20Sopenharmony_ci - Andre Przywara <andre.przywara@arm.com> 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ciproperties: 188c2ecf20Sopenharmony_ci compatible: 198c2ecf20Sopenharmony_ci enum: 208c2ecf20Sopenharmony_ci - calxeda,hb-ddr-ctrl 218c2ecf20Sopenharmony_ci - calxeda,ecx-2000-ddr-ctrl 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci reg: 248c2ecf20Sopenharmony_ci maxItems: 1 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ci interrupts: 278c2ecf20Sopenharmony_ci maxItems: 1 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_cirequired: 308c2ecf20Sopenharmony_ci - compatible 318c2ecf20Sopenharmony_ci - reg 328c2ecf20Sopenharmony_ci - interrupts 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_ciadditionalProperties: false 358c2ecf20Sopenharmony_ci 368c2ecf20Sopenharmony_ciexamples: 378c2ecf20Sopenharmony_ci - | 388c2ecf20Sopenharmony_ci memory-controller@fff00000 { 398c2ecf20Sopenharmony_ci compatible = "calxeda,hb-ddr-ctrl"; 408c2ecf20Sopenharmony_ci reg = <0xfff00000 0x1000>; 418c2ecf20Sopenharmony_ci interrupts = <0 91 4>; 428c2ecf20Sopenharmony_ci }; 43