18c2ecf20Sopenharmony_ciDDR PHY Front End (DPFE) for Broadcom STB 28c2ecf20Sopenharmony_ci========================================= 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ciDPFE and the DPFE firmware provide an interface for the host CPU to 58c2ecf20Sopenharmony_cicommunicate with the DCPU, which resides inside the DDR PHY. 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciThere are three memory regions for interacting with the DCPU. These are 88c2ecf20Sopenharmony_cispecified in a single reg property. 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ciRequired properties: 118c2ecf20Sopenharmony_ci - compatible: must be "brcm,bcm7271-dpfe-cpu", "brcm,bcm7268-dpfe-cpu" 128c2ecf20Sopenharmony_ci or "brcm,dpfe-cpu" 138c2ecf20Sopenharmony_ci - reg: must reference three register ranges 148c2ecf20Sopenharmony_ci - start address and length of the DCPU register space 158c2ecf20Sopenharmony_ci - start address and length of the DCPU data memory space 168c2ecf20Sopenharmony_ci - start address and length of the DCPU instruction memory space 178c2ecf20Sopenharmony_ci - reg-names: must contain "dpfe-cpu", "dpfe-dmem", and "dpfe-imem"; 188c2ecf20Sopenharmony_ci they must be in the same order as the register declarations 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ciExample: 218c2ecf20Sopenharmony_ci dpfe_cpu0: dpfe-cpu@f1132000 { 228c2ecf20Sopenharmony_ci compatible = "brcm,bcm7271-dpfe-cpu", "brcm,dpfe-cpu"; 238c2ecf20Sopenharmony_ci reg = <0xf1132000 0x180 248c2ecf20Sopenharmony_ci 0xf1134000 0x1000 258c2ecf20Sopenharmony_ci 0xf1138000 0x4000>; 268c2ecf20Sopenharmony_ci reg-names = "dpfe-cpu", "dpfe-dmem", "dpfe-imem"; 278c2ecf20Sopenharmony_ci }; 28