18c2ecf20Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 28c2ecf20Sopenharmony_ci%YAML 1.2 38c2ecf20Sopenharmony_ci--- 48c2ecf20Sopenharmony_ci$id: http://devicetree.org/schemas/media/renesas,fdp1.yaml# 58c2ecf20Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_cititle: Renesas R-Car Fine Display Processor (FDP1) 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_cimaintainers: 108c2ecf20Sopenharmony_ci - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_cidescription: 138c2ecf20Sopenharmony_ci The FDP1 is a de-interlacing module which converts interlaced video to 148c2ecf20Sopenharmony_ci progressive video. It is capable of performing pixel format conversion 158c2ecf20Sopenharmony_ci between YCbCr/YUV formats and RGB formats. Only YCbCr/YUV formats are 168c2ecf20Sopenharmony_ci supported as an input to the module. 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ciproperties: 198c2ecf20Sopenharmony_ci compatible: 208c2ecf20Sopenharmony_ci enum: 218c2ecf20Sopenharmony_ci - renesas,fdp1 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci reg: 248c2ecf20Sopenharmony_ci maxItems: 1 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ci interrupts: 278c2ecf20Sopenharmony_ci maxItems: 1 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ci clocks: 308c2ecf20Sopenharmony_ci maxItems: 1 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ci power-domains: 338c2ecf20Sopenharmony_ci maxItems: 1 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_ci resets: 368c2ecf20Sopenharmony_ci maxItems: 1 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ci renesas,fcp: 398c2ecf20Sopenharmony_ci $ref: /schemas/types.yaml#/definitions/phandle 408c2ecf20Sopenharmony_ci description: 418c2ecf20Sopenharmony_ci A phandle referencing the FCP that handles memory accesses for the FDP1. 428c2ecf20Sopenharmony_ci Not allowed on R-Car Gen2, mandatory on R-Car Gen3. 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_cirequired: 458c2ecf20Sopenharmony_ci - compatible 468c2ecf20Sopenharmony_ci - reg 478c2ecf20Sopenharmony_ci - interrupts 488c2ecf20Sopenharmony_ci - clocks 498c2ecf20Sopenharmony_ci - power-domains 508c2ecf20Sopenharmony_ci - resets 518c2ecf20Sopenharmony_ci 528c2ecf20Sopenharmony_ciadditionalProperties: false 538c2ecf20Sopenharmony_ci 548c2ecf20Sopenharmony_ciexamples: 558c2ecf20Sopenharmony_ci - | 568c2ecf20Sopenharmony_ci #include <dt-bindings/clock/renesas-cpg-mssr.h> 578c2ecf20Sopenharmony_ci #include <dt-bindings/interrupt-controller/arm-gic.h> 588c2ecf20Sopenharmony_ci #include <dt-bindings/power/r8a7795-sysc.h> 598c2ecf20Sopenharmony_ci 608c2ecf20Sopenharmony_ci fdp1@fe940000 { 618c2ecf20Sopenharmony_ci compatible = "renesas,fdp1"; 628c2ecf20Sopenharmony_ci reg = <0xfe940000 0x2400>; 638c2ecf20Sopenharmony_ci interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 648c2ecf20Sopenharmony_ci clocks = <&cpg CPG_MOD 119>; 658c2ecf20Sopenharmony_ci power-domains = <&sysc R8A7795_PD_A3VP>; 668c2ecf20Sopenharmony_ci resets = <&cpg 119>; 678c2ecf20Sopenharmony_ci renesas,fcp = <&fcpf0>; 688c2ecf20Sopenharmony_ci }; 698c2ecf20Sopenharmony_ci... 70