18c2ecf20Sopenharmony_ciFreescale i.MX7 Mipi CSI2
28c2ecf20Sopenharmony_ci=========================
38c2ecf20Sopenharmony_ci
48c2ecf20Sopenharmony_cimipi_csi2 node
58c2ecf20Sopenharmony_ci--------------
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_ciThis is the device node for the MIPI CSI-2 receiver core in i.MX7 SoC. It is
88c2ecf20Sopenharmony_cicompatible with previous version of Samsung D-phy.
98c2ecf20Sopenharmony_ci
108c2ecf20Sopenharmony_ciRequired properties:
118c2ecf20Sopenharmony_ci
128c2ecf20Sopenharmony_ci- compatible    : "fsl,imx7-mipi-csi2";
138c2ecf20Sopenharmony_ci- reg           : base address and length of the register set for the device;
148c2ecf20Sopenharmony_ci- interrupts    : should contain MIPI CSIS interrupt;
158c2ecf20Sopenharmony_ci- clocks        : list of clock specifiers, see
168c2ecf20Sopenharmony_ci        Documentation/devicetree/bindings/clock/clock-bindings.txt for details;
178c2ecf20Sopenharmony_ci- clock-names   : must contain "pclk", "wrap" and "phy" entries, matching
188c2ecf20Sopenharmony_ci                  entries in the clock property;
198c2ecf20Sopenharmony_ci- power-domains : a phandle to the power domain, see
208c2ecf20Sopenharmony_ci          Documentation/devicetree/bindings/power/power_domain.txt for details.
218c2ecf20Sopenharmony_ci- reset-names   : should include following entry "mrst";
228c2ecf20Sopenharmony_ci- resets        : a list of phandle, should contain reset entry of
238c2ecf20Sopenharmony_ci                  reset-names;
248c2ecf20Sopenharmony_ci- phy-supply    : from the generic phy bindings, a phandle to a regulator that
258c2ecf20Sopenharmony_ci	          provides power to MIPI CSIS core;
268c2ecf20Sopenharmony_ci
278c2ecf20Sopenharmony_ciOptional properties:
288c2ecf20Sopenharmony_ci
298c2ecf20Sopenharmony_ci- clock-frequency : The IP's main (system bus) clock frequency in Hz, default
308c2ecf20Sopenharmony_ci		    value when this property is not specified is 166 MHz;
318c2ecf20Sopenharmony_ci- fsl,csis-hs-settle : differential receiver (HS-RX) settle time;
328c2ecf20Sopenharmony_ci
338c2ecf20Sopenharmony_ciThe device node should contain two 'port' child nodes with one child 'endpoint'
348c2ecf20Sopenharmony_cinode, according to the bindings defined in:
358c2ecf20Sopenharmony_ci Documentation/devicetree/bindings/ media/video-interfaces.txt.
368c2ecf20Sopenharmony_ci The following are properties specific to those nodes.
378c2ecf20Sopenharmony_ci
388c2ecf20Sopenharmony_ciport node
398c2ecf20Sopenharmony_ci---------
408c2ecf20Sopenharmony_ci
418c2ecf20Sopenharmony_ci- reg		  : (required) can take the values 0 or 1, where 0 shall be
428c2ecf20Sopenharmony_ci                     related to the sink port and port 1 shall be the source
438c2ecf20Sopenharmony_ci                     one;
448c2ecf20Sopenharmony_ci
458c2ecf20Sopenharmony_ciendpoint node
468c2ecf20Sopenharmony_ci-------------
478c2ecf20Sopenharmony_ci
488c2ecf20Sopenharmony_ci- data-lanes    : (required) an array specifying active physical MIPI-CSI2
498c2ecf20Sopenharmony_ci		    data input lanes and their mapping to logical lanes; this
508c2ecf20Sopenharmony_ci                    shall only be applied to port 0 (sink port), the array's
518c2ecf20Sopenharmony_ci                    content is unused only its length is meaningful,
528c2ecf20Sopenharmony_ci                    in this case the maximum length supported is 2;
538c2ecf20Sopenharmony_ci
548c2ecf20Sopenharmony_ciexample:
558c2ecf20Sopenharmony_ci
568c2ecf20Sopenharmony_ci        mipi_csi: mipi-csi@30750000 {
578c2ecf20Sopenharmony_ci                #address-cells = <1>;
588c2ecf20Sopenharmony_ci                #size-cells = <0>;
598c2ecf20Sopenharmony_ci
608c2ecf20Sopenharmony_ci                compatible = "fsl,imx7-mipi-csi2";
618c2ecf20Sopenharmony_ci                reg = <0x30750000 0x10000>;
628c2ecf20Sopenharmony_ci                interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
638c2ecf20Sopenharmony_ci                clocks = <&clks IMX7D_IPG_ROOT_CLK>,
648c2ecf20Sopenharmony_ci                                <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
658c2ecf20Sopenharmony_ci                                <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
668c2ecf20Sopenharmony_ci                clock-names = "pclk", "wrap", "phy";
678c2ecf20Sopenharmony_ci                clock-frequency = <166000000>;
688c2ecf20Sopenharmony_ci                power-domains = <&pgc_mipi_phy>;
698c2ecf20Sopenharmony_ci                phy-supply = <&reg_1p0d>;
708c2ecf20Sopenharmony_ci                resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
718c2ecf20Sopenharmony_ci                reset-names = "mrst";
728c2ecf20Sopenharmony_ci                fsl,csis-hs-settle = <3>;
738c2ecf20Sopenharmony_ci
748c2ecf20Sopenharmony_ci                port@0 {
758c2ecf20Sopenharmony_ci                        reg = <0>;
768c2ecf20Sopenharmony_ci
778c2ecf20Sopenharmony_ci                        mipi_from_sensor: endpoint {
788c2ecf20Sopenharmony_ci                                remote-endpoint = <&ov2680_to_mipi>;
798c2ecf20Sopenharmony_ci                                data-lanes = <1>;
808c2ecf20Sopenharmony_ci                        };
818c2ecf20Sopenharmony_ci                };
828c2ecf20Sopenharmony_ci
838c2ecf20Sopenharmony_ci                port@1 {
848c2ecf20Sopenharmony_ci                        reg = <1>;
858c2ecf20Sopenharmony_ci
868c2ecf20Sopenharmony_ci                        mipi_vc0_to_csi_mux: endpoint {
878c2ecf20Sopenharmony_ci                                remote-endpoint = <&csi_mux_from_mipi_vc0>;
888c2ecf20Sopenharmony_ci                        };
898c2ecf20Sopenharmony_ci                };
908c2ecf20Sopenharmony_ci        };
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