18c2ecf20Sopenharmony_ciFreescale Pixel Pipeline 28c2ecf20Sopenharmony_ci======================== 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ciThe Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine 58c2ecf20Sopenharmony_cithat supports scaling, colorspace conversion, alpha blending, rotation, and 68c2ecf20Sopenharmony_cipixel conversion via lookup table. Different versions are present on various 78c2ecf20Sopenharmony_cii.MX SoCs from i.MX23 to i.MX7. 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ciRequired properties: 108c2ecf20Sopenharmony_ci- compatible: should be "fsl,<soc>-pxp", where SoC can be one of imx23, imx28, 118c2ecf20Sopenharmony_ci imx6dl, imx6sl, imx6sll, imx6ul, imx6sx, imx6ull, or imx7d. 128c2ecf20Sopenharmony_ci- reg: the register base and size for the device registers 138c2ecf20Sopenharmony_ci- interrupts: the PXP interrupt, two interrupts for imx6ull and imx7d. 148c2ecf20Sopenharmony_ci- clock-names: should be "axi" 158c2ecf20Sopenharmony_ci- clocks: the PXP AXI clock 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ciExample: 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_cipxp@21cc000 { 208c2ecf20Sopenharmony_ci compatible = "fsl,imx6ull-pxp"; 218c2ecf20Sopenharmony_ci reg = <0x021cc000 0x4000>; 228c2ecf20Sopenharmony_ci interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 238c2ecf20Sopenharmony_ci <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 248c2ecf20Sopenharmony_ci clock-names = "axi"; 258c2ecf20Sopenharmony_ci clocks = <&clks IMX6UL_CLK_PXP>; 268c2ecf20Sopenharmony_ci}; 27