18c2ecf20Sopenharmony_ciRockchip mailbox 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThe Rockchip mailbox is used by the Rockchip CPU cores to communicate 48c2ecf20Sopenharmony_cirequests to MCU processor. 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ciRefer to ./mailbox.txt for generic information about mailbox device-tree 78c2ecf20Sopenharmony_cibindings. 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ciRequired properties: 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci - compatible: should be one of the following. 128c2ecf20Sopenharmony_ci - "rockchip,rk3368-mbox" for rk3368 138c2ecf20Sopenharmony_ci - reg: physical base address of the controller and length of memory mapped 148c2ecf20Sopenharmony_ci region. 158c2ecf20Sopenharmony_ci - interrupts: The interrupt number to the cpu. The interrupt specifier format 168c2ecf20Sopenharmony_ci depends on the interrupt controller. 178c2ecf20Sopenharmony_ci - #mbox-cells: Common mailbox binding property to identify the number 188c2ecf20Sopenharmony_ci of cells required for the mailbox specifier. Should be 1 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ciExample: 218c2ecf20Sopenharmony_ci-------- 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci/* RK3368 */ 248c2ecf20Sopenharmony_cimbox: mbox@ff6b0000 { 258c2ecf20Sopenharmony_ci compatible = "rockchip,rk3368-mailbox"; 268c2ecf20Sopenharmony_ci reg = <0x0 0xff6b0000 0x0 0x1000>, 278c2ecf20Sopenharmony_ci interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 288c2ecf20Sopenharmony_ci <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 298c2ecf20Sopenharmony_ci <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 308c2ecf20Sopenharmony_ci <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 318c2ecf20Sopenharmony_ci #mbox-cells = <1>; 328c2ecf20Sopenharmony_ci}; 33