18c2ecf20Sopenharmony_ciThe PDC driver manages data transfer to and from various offload engines 28c2ecf20Sopenharmony_cion some Broadcom SoCs. An SoC may have multiple PDC hardware blocks. There is 38c2ecf20Sopenharmony_cione device tree entry per block. On some chips, the PDC functionality is 48c2ecf20Sopenharmony_cihandled by the FA2 (Northstar Plus). 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ciRequired properties: 78c2ecf20Sopenharmony_ci- compatible : Should be "brcm,iproc-pdc-mbox" or "brcm,iproc-fa2-mbox" for 88c2ecf20Sopenharmony_ci FA2/Northstar Plus. 98c2ecf20Sopenharmony_ci- reg: Should contain PDC registers location and length. 108c2ecf20Sopenharmony_ci- interrupts: Should contain the IRQ line for the PDC. 118c2ecf20Sopenharmony_ci- #mbox-cells: 1 128c2ecf20Sopenharmony_ci- brcm,rx-status-len: Length of metadata preceding received frames, in bytes. 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ciOptional properties: 158c2ecf20Sopenharmony_ci- brcm,use-bcm-hdr: present if a BCM header precedes each frame. 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ciExample: 188c2ecf20Sopenharmony_ci pdc0: iproc-pdc0@612c0000 { 198c2ecf20Sopenharmony_ci compatible = "brcm,iproc-pdc-mbox"; 208c2ecf20Sopenharmony_ci reg = <0 0x612c0000 0 0x445>; /* PDC FS0 regs */ 218c2ecf20Sopenharmony_ci interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 228c2ecf20Sopenharmony_ci #mbox-cells = <1>; /* one cell per mailbox channel */ 238c2ecf20Sopenharmony_ci brcm,rx-status-len = <32>; 248c2ecf20Sopenharmony_ci brcm,use-bcm-hdr; 258c2ecf20Sopenharmony_ci }; 26