18c2ecf20Sopenharmony_ciNVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit) 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciRequired properties: 48c2ecf20Sopenharmony_ci- compatible : "nvidia,tegra30-smmu" 58c2ecf20Sopenharmony_ci- reg : Should contain 3 register banks(address and length) for each 68c2ecf20Sopenharmony_ci of the SMMU register blocks. 78c2ecf20Sopenharmony_ci- interrupts : Should contain MC General interrupt. 88c2ecf20Sopenharmony_ci- nvidia,#asids : # of ASIDs 98c2ecf20Sopenharmony_ci- dma-window : IOVA start address and length. 108c2ecf20Sopenharmony_ci- nvidia,ahb : phandle to the ahb bus connected to SMMU. 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ciExample: 138c2ecf20Sopenharmony_ci smmu { 148c2ecf20Sopenharmony_ci compatible = "nvidia,tegra30-smmu"; 158c2ecf20Sopenharmony_ci reg = <0x7000f010 0x02c 168c2ecf20Sopenharmony_ci 0x7000f1f0 0x010 178c2ecf20Sopenharmony_ci 0x7000f228 0x05c>; 188c2ecf20Sopenharmony_ci nvidia,#asids = <4>; /* # of ASIDs */ 198c2ecf20Sopenharmony_ci dma-window = <0 0x40000000>; /* IOVA start & length */ 208c2ecf20Sopenharmony_ci nvidia,ahb = <&ahb>; 218c2ecf20Sopenharmony_ci }; 22