18c2ecf20Sopenharmony_ciOmap2/3 intc controller
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciOn TI omap2 and 3 the intc interrupt controller can provide
48c2ecf20Sopenharmony_ci96 or 128 IRQ signals to the ARM host depending on the SoC.
58c2ecf20Sopenharmony_ci
68c2ecf20Sopenharmony_ciRequired Properties:
78c2ecf20Sopenharmony_ci- compatible: should be one of
88c2ecf20Sopenharmony_ci			"ti,omap2-intc"
98c2ecf20Sopenharmony_ci			"ti,omap3-intc"
108c2ecf20Sopenharmony_ci			"ti,dm814-intc"
118c2ecf20Sopenharmony_ci			"ti,dm816-intc"
128c2ecf20Sopenharmony_ci			"ti,am33xx-intc"
138c2ecf20Sopenharmony_ci
148c2ecf20Sopenharmony_ci- interrupt-controller : Identifies the node as an interrupt controller
158c2ecf20Sopenharmony_ci- #interrupt-cells : Specifies the number of cells needed to encode interrupt
168c2ecf20Sopenharmony_ci		     source, should be 1 for intc
178c2ecf20Sopenharmony_ci- interrupts: interrupt reference to primary interrupt controller
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ciPlease refer to interrupts.txt in this directory for details of the common
208c2ecf20Sopenharmony_ciInterrupt Controllers bindings used by client devices.
218c2ecf20Sopenharmony_ci
228c2ecf20Sopenharmony_ciExample:
238c2ecf20Sopenharmony_ci	intc: interrupt-controller@48200000 {
248c2ecf20Sopenharmony_ci		compatible = "ti,omap3-intc";
258c2ecf20Sopenharmony_ci		interrupt-controller;
268c2ecf20Sopenharmony_ci		#interrupt-cells = <1>;
278c2ecf20Sopenharmony_ci		reg = <0x48200000 0x1000>;
288c2ecf20Sopenharmony_ci	};
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