18c2ecf20Sopenharmony_ciTS-4800 FPGA interrupt controller
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciTS-4800 FPGA has an internal interrupt controller. When one of the
48c2ecf20Sopenharmony_ciinterrupts is triggered, the SoC is notified, usually using a GPIO as
58c2ecf20Sopenharmony_ciparent interrupt source.
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_ciRequired properties:
88c2ecf20Sopenharmony_ci- compatible: should be "technologic,ts4800-irqc"
98c2ecf20Sopenharmony_ci- interrupt-controller: identifies the node as an interrupt controller
108c2ecf20Sopenharmony_ci- reg: physical base address of the controller and length of memory mapped
118c2ecf20Sopenharmony_ci  region
128c2ecf20Sopenharmony_ci- #interrupt-cells: specifies the number of cells needed to encode an interrupt
138c2ecf20Sopenharmony_ci  source, should be 1.
148c2ecf20Sopenharmony_ci- interrupts: specifies the interrupt line in the interrupt-parent controller
15