18c2ecf20Sopenharmony_ciSynopsys DesignWare APB interrupt controller (dw_apb_ictl) 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciSynopsys DesignWare provides interrupt controller IP for APB known as 48c2ecf20Sopenharmony_cidw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with 58c2ecf20Sopenharmony_ciAPB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt 68c2ecf20Sopenharmony_cicontroller in some SoCs, e.g. Hisilicon SD5203. 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ciRequired properties: 98c2ecf20Sopenharmony_ci- compatible: shall be "snps,dw-apb-ictl" 108c2ecf20Sopenharmony_ci- reg: physical base address of the controller and length of memory mapped 118c2ecf20Sopenharmony_ci region starting with ENABLE_LOW register 128c2ecf20Sopenharmony_ci- interrupt-controller: identifies the node as an interrupt controller 138c2ecf20Sopenharmony_ci- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ciAdditional required property when it's used as secondary interrupt controller: 168c2ecf20Sopenharmony_ci- interrupts: interrupt reference to primary interrupt controller 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ciThe interrupt sources map to the corresponding bits in the interrupt 198c2ecf20Sopenharmony_ciregisters, i.e. 208c2ecf20Sopenharmony_ci- 0 maps to bit 0 of low interrupts, 218c2ecf20Sopenharmony_ci- 1 maps to bit 1 of low interrupts, 228c2ecf20Sopenharmony_ci- 32 maps to bit 0 of high interrupts, 238c2ecf20Sopenharmony_ci- 33 maps to bit 1 of high interrupts, 248c2ecf20Sopenharmony_ci- (optional) fast interrupts start at 64. 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ciExample: 278c2ecf20Sopenharmony_ci /* dw_apb_ictl is used as secondary interrupt controller */ 288c2ecf20Sopenharmony_ci aic: interrupt-controller@3000 { 298c2ecf20Sopenharmony_ci compatible = "snps,dw-apb-ictl"; 308c2ecf20Sopenharmony_ci reg = <0x3000 0xc00>; 318c2ecf20Sopenharmony_ci interrupt-controller; 328c2ecf20Sopenharmony_ci #interrupt-cells = <1>; 338c2ecf20Sopenharmony_ci interrupt-parent = <&gic>; 348c2ecf20Sopenharmony_ci interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 358c2ecf20Sopenharmony_ci }; 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_ci /* dw_apb_ictl is used as primary interrupt controller */ 388c2ecf20Sopenharmony_ci vic: interrupt-controller@10130000 { 398c2ecf20Sopenharmony_ci compatible = "snps,dw-apb-ictl"; 408c2ecf20Sopenharmony_ci reg = <0x10130000 0x1000>; 418c2ecf20Sopenharmony_ci interrupt-controller; 428c2ecf20Sopenharmony_ci #interrupt-cells = <1>; 438c2ecf20Sopenharmony_ci }; 44