18c2ecf20Sopenharmony_ciPDC interrupt controller
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciQualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
48c2ecf20Sopenharmony_ciPower Domain Controller (PDC) that is on always-on domain. In addition to
58c2ecf20Sopenharmony_ciproviding power control for the power domains, the hardware also has an
68c2ecf20Sopenharmony_ciinterrupt controller that can be used to help detect edge low interrupts as
78c2ecf20Sopenharmony_ciwell detect interrupts when the GIC is non-operational.
88c2ecf20Sopenharmony_ci
98c2ecf20Sopenharmony_ciGIC is parent interrupt controller at the highest level. Platform interrupt
108c2ecf20Sopenharmony_cicontroller PDC is next in hierarchy, followed by others. Drivers requiring
118c2ecf20Sopenharmony_ciwakeup capabilities of their device interrupts routed through the PDC, must
128c2ecf20Sopenharmony_cispecify PDC as their interrupt controller and request the PDC port associated
138c2ecf20Sopenharmony_ciwith the GIC interrupt. See example below.
148c2ecf20Sopenharmony_ci
158c2ecf20Sopenharmony_ciProperties:
168c2ecf20Sopenharmony_ci
178c2ecf20Sopenharmony_ci- compatible:
188c2ecf20Sopenharmony_ci	Usage: required
198c2ecf20Sopenharmony_ci	Value type: <string>
208c2ecf20Sopenharmony_ci	Definition: Should contain "qcom,<soc>-pdc" and "qcom,pdc"
218c2ecf20Sopenharmony_ci		    - "qcom,sc7180-pdc": For SC7180
228c2ecf20Sopenharmony_ci		    - "qcom,sdm845-pdc": For SDM845
238c2ecf20Sopenharmony_ci
248c2ecf20Sopenharmony_ci- reg:
258c2ecf20Sopenharmony_ci	Usage: required
268c2ecf20Sopenharmony_ci	Value type: <prop-encoded-array>
278c2ecf20Sopenharmony_ci	Definition: Specifies the base physical address for PDC hardware.
288c2ecf20Sopenharmony_ci
298c2ecf20Sopenharmony_ci- interrupt-cells:
308c2ecf20Sopenharmony_ci	Usage: required
318c2ecf20Sopenharmony_ci	Value type: <u32>
328c2ecf20Sopenharmony_ci	Definition: Specifies the number of cells needed to encode an interrupt
338c2ecf20Sopenharmony_ci		    source.
348c2ecf20Sopenharmony_ci		    Must be 2.
358c2ecf20Sopenharmony_ci		    The first element of the tuple is the PDC pin for the
368c2ecf20Sopenharmony_ci		    interrupt.
378c2ecf20Sopenharmony_ci		    The second element is the trigger type.
388c2ecf20Sopenharmony_ci
398c2ecf20Sopenharmony_ci- interrupt-controller:
408c2ecf20Sopenharmony_ci	Usage: required
418c2ecf20Sopenharmony_ci	Value type: <bool>
428c2ecf20Sopenharmony_ci	Definition: Identifies the node as an interrupt controller.
438c2ecf20Sopenharmony_ci
448c2ecf20Sopenharmony_ci- qcom,pdc-ranges:
458c2ecf20Sopenharmony_ci	Usage: required
468c2ecf20Sopenharmony_ci	Value type: <u32 array>
478c2ecf20Sopenharmony_ci	Definition: Specifies the PDC pin offset and the number of PDC ports.
488c2ecf20Sopenharmony_ci		    The tuples indicates the valid mapping of valid PDC ports
498c2ecf20Sopenharmony_ci		    and their hwirq mapping.
508c2ecf20Sopenharmony_ci		    The first element of the tuple is the starting PDC port.
518c2ecf20Sopenharmony_ci		    The second element is the GIC hwirq number for the PDC port.
528c2ecf20Sopenharmony_ci		    The third element is the number of interrupts in sequence.
538c2ecf20Sopenharmony_ci
548c2ecf20Sopenharmony_ciExample:
558c2ecf20Sopenharmony_ci
568c2ecf20Sopenharmony_ci	pdc: interrupt-controller@b220000 {
578c2ecf20Sopenharmony_ci		compatible = "qcom,sdm845-pdc";
588c2ecf20Sopenharmony_ci		reg = <0xb220000 0x30000>;
598c2ecf20Sopenharmony_ci		qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
608c2ecf20Sopenharmony_ci		#interrupt-cells = <2>;
618c2ecf20Sopenharmony_ci		interrupt-parent = <&intc>;
628c2ecf20Sopenharmony_ci		interrupt-controller;
638c2ecf20Sopenharmony_ci	};
648c2ecf20Sopenharmony_ci
658c2ecf20Sopenharmony_ciDT binding of a device that wants to use the GIC SPI 514 as a wakeup
668c2ecf20Sopenharmony_ciinterrupt, must do -
678c2ecf20Sopenharmony_ci
688c2ecf20Sopenharmony_ci	wake-device {
698c2ecf20Sopenharmony_ci		interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;
708c2ecf20Sopenharmony_ci	};
718c2ecf20Sopenharmony_ci
728c2ecf20Sopenharmony_ciIn this case interrupt 514 would be mapped to port 2 on the PDC as defined by
738c2ecf20Sopenharmony_cithe qcom,pdc-ranges property.
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