18c2ecf20Sopenharmony_ciOpen Multi-Processor Interrupt Controller
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38c2ecf20Sopenharmony_ciRequired properties:
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58c2ecf20Sopenharmony_ci- compatible : This should be "openrisc,ompic"
68c2ecf20Sopenharmony_ci- reg : Specifies base physical address and size of the register space. The
78c2ecf20Sopenharmony_ci  size is based on the number of cores the controller has been configured
88c2ecf20Sopenharmony_ci  to handle, this should be set to 8 bytes per cpu core.
98c2ecf20Sopenharmony_ci- interrupt-controller : Identifies the node as an interrupt controller.
108c2ecf20Sopenharmony_ci- #interrupt-cells : This should be set to 0 as this will not be an irq
118c2ecf20Sopenharmony_ci  parent.
128c2ecf20Sopenharmony_ci- interrupts : Specifies the interrupt line to which the ompic is wired.
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148c2ecf20Sopenharmony_ciExample:
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168c2ecf20Sopenharmony_ciompic: interrupt-controller@98000000 {
178c2ecf20Sopenharmony_ci	compatible = "openrisc,ompic";
188c2ecf20Sopenharmony_ci	reg = <0x98000000 16>;
198c2ecf20Sopenharmony_ci	interrupt-controller;
208c2ecf20Sopenharmony_ci	#interrupt-cells = <0>;
218c2ecf20Sopenharmony_ci	interrupts = <1>;
228c2ecf20Sopenharmony_ci};
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