18c2ecf20Sopenharmony_ciMarvell Armada 7K/8K PIC Interrupt controller 28c2ecf20Sopenharmony_ci--------------------------------------------- 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ciThis is the Device Tree binding for the PIC, a secondary interrupt 58c2ecf20Sopenharmony_cicontroller available on the Marvell Armada 7K/8K ARM64 SoCs, and 68c2ecf20Sopenharmony_citypically connected to the GIC as the primary interrupt controller. 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ciRequired properties: 98c2ecf20Sopenharmony_ci- compatible: should be "marvell,armada-8k-pic" 108c2ecf20Sopenharmony_ci- interrupt-controller: identifies the node as an interrupt controller 118c2ecf20Sopenharmony_ci- #interrupt-cells: the number of cells to define interrupts on this 128c2ecf20Sopenharmony_ci controller. Should be 1 138c2ecf20Sopenharmony_ci- reg: the register area for the PIC interrupt controller 148c2ecf20Sopenharmony_ci- interrupts: the interrupt to the primary interrupt controller, 158c2ecf20Sopenharmony_ci typically the GIC 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ciExample: 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ci pic: interrupt-controller@3f0100 { 208c2ecf20Sopenharmony_ci compatible = "marvell,armada-8k-pic"; 218c2ecf20Sopenharmony_ci reg = <0x3f0100 0x10>; 228c2ecf20Sopenharmony_ci #interrupt-cells = <1>; 238c2ecf20Sopenharmony_ci interrupt-controller; 248c2ecf20Sopenharmony_ci interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 258c2ecf20Sopenharmony_ci }; 26