18c2ecf20Sopenharmony_ciInterrupt chips 28c2ecf20Sopenharmony_ci--------------- 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ci* Intel I/O Advanced Programmable Interrupt Controller (IO APIC) 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ci Required properties: 78c2ecf20Sopenharmony_ci -------------------- 88c2ecf20Sopenharmony_ci compatible = "intel,ce4100-ioapic"; 98c2ecf20Sopenharmony_ci #interrupt-cells = <2>; 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci Device's interrupt property: 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci interrupts = <P S>; 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci The first number (P) represents the interrupt pin which is wired to the 168c2ecf20Sopenharmony_ci IO APIC. The second number (S) represents the sense of interrupt which 178c2ecf20Sopenharmony_ci should be configured and can be one of: 188c2ecf20Sopenharmony_ci 0 - Edge Rising 198c2ecf20Sopenharmony_ci 1 - Level Low 208c2ecf20Sopenharmony_ci 2 - Level High 218c2ecf20Sopenharmony_ci 3 - Edge Falling 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci* Local APIC 248c2ecf20Sopenharmony_ci Required property: 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ci compatible = "intel,ce4100-lapic"; 27