18c2ecf20Sopenharmony_ci* ARM Nested Vector Interrupt Controller (NVIC) 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThe NVIC provides an interrupt controller that is tightly coupled to 48c2ecf20Sopenharmony_ciCortex-M based processor cores. The NVIC implemented on different SoCs 58c2ecf20Sopenharmony_civary in the number of interrupts and priority bits per interrupt. 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciMain node required properties: 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci- compatible : should be one of: 108c2ecf20Sopenharmony_ci "arm,v6m-nvic" 118c2ecf20Sopenharmony_ci "arm,v7m-nvic" 128c2ecf20Sopenharmony_ci "arm,v8m-nvic" 138c2ecf20Sopenharmony_ci- interrupt-controller : Identifies the node as an interrupt controller 148c2ecf20Sopenharmony_ci- #interrupt-cells : Specifies the number of cells needed to encode an 158c2ecf20Sopenharmony_ci interrupt source. The type shall be a <u32> and the value shall be 2. 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci The 1st cell contains the interrupt number for the interrupt type. 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ci The 2nd cell is the priority of the interrupt. 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ci- reg : Specifies base physical address(s) and size of the NVIC registers. 228c2ecf20Sopenharmony_ci This is at a fixed address (0xe000e100) and size (0xc00). 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ci- arm,num-irq-priority-bits: The number of priority bits implemented by the 258c2ecf20Sopenharmony_ci given SoC 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ciExample: 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ci intc: interrupt-controller@e000e100 { 308c2ecf20Sopenharmony_ci compatible = "arm,v7m-nvic"; 318c2ecf20Sopenharmony_ci #interrupt-cells = <2>; 328c2ecf20Sopenharmony_ci #address-cells = <1>; 338c2ecf20Sopenharmony_ci interrupt-controller; 348c2ecf20Sopenharmony_ci reg = <0xe000e100 0xc00>; 358c2ecf20Sopenharmony_ci arm,num-irq-priority-bits = <4>; 368c2ecf20Sopenharmony_ci }; 37