18c2ecf20Sopenharmony_ciAlpine MSIX controller 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciSee arm,gic-v3.txt for SPI and MSI definitions. 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ciRequired properties: 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ci- compatible: should be "al,alpine-msix" 88c2ecf20Sopenharmony_ci- reg: physical base address and size of the registers 98c2ecf20Sopenharmony_ci- interrupt-controller: identifies the node as an interrupt controller 108c2ecf20Sopenharmony_ci- msi-controller: identifies the node as an PCI Message Signaled Interrupt 118c2ecf20Sopenharmony_ci controller 128c2ecf20Sopenharmony_ci- al,msi-base-spi: SPI base of the MSI frame 138c2ecf20Sopenharmony_ci- al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ciExample: 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_cimsix: msix { 188c2ecf20Sopenharmony_ci compatible = "al,alpine-msix"; 198c2ecf20Sopenharmony_ci reg = <0x0 0xfbe00000 0x0 0x100000>; 208c2ecf20Sopenharmony_ci interrupt-parent = <&gic>; 218c2ecf20Sopenharmony_ci interrupt-controller; 228c2ecf20Sopenharmony_ci msi-controller; 238c2ecf20Sopenharmony_ci al,msi-base-spi = <160>; 248c2ecf20Sopenharmony_ci al,msi-num-spis = <160>; 258c2ecf20Sopenharmony_ci}; 26