18c2ecf20Sopenharmony_ciAnalog Devices AD2S90 Resolver-to-Digital Converter 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_cihttps://www.analog.com/en/products/ad2s90.html 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ciRequired properties: 68c2ecf20Sopenharmony_ci - compatible: should be "adi,ad2s90" 78c2ecf20Sopenharmony_ci - reg: SPI chip select number for the device 88c2ecf20Sopenharmony_ci - spi-max-frequency: set maximum clock frequency, must be 830000 98c2ecf20Sopenharmony_ci - spi-cpol and spi-cpha: 108c2ecf20Sopenharmony_ci Either SPI mode (0,0) or (1,1) must be used, so specify none or both of 118c2ecf20Sopenharmony_ci spi-cpha, spi-cpol. 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ciSee for more details: 148c2ecf20Sopenharmony_ci Documentation/devicetree/bindings/spi/spi-bus.txt 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ciNote about max frequency: 178c2ecf20Sopenharmony_ci Chip's max frequency, as specified in its datasheet, is 2Mhz. But a 600ns 188c2ecf20Sopenharmony_ci delay is expected between the application of a logic LO to CS and the 198c2ecf20Sopenharmony_ci application of SCLK, as also specified. And since the delay is not 208c2ecf20Sopenharmony_ci implemented in the spi code, to satisfy it, SCLK's period should be at most 218c2ecf20Sopenharmony_ci 2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which gives 228c2ecf20Sopenharmony_ci roughly 830000Hz. 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ciExample: 258c2ecf20Sopenharmony_ciresolver@0 { 268c2ecf20Sopenharmony_ci compatible = "adi,ad2s90"; 278c2ecf20Sopenharmony_ci reg = <0>; 288c2ecf20Sopenharmony_ci spi-max-frequency = <830000>; 298c2ecf20Sopenharmony_ci spi-cpol; 308c2ecf20Sopenharmony_ci spi-cpha; 318c2ecf20Sopenharmony_ci}; 32