18c2ecf20Sopenharmony_ciRockchip RK3328 GRF (General Register Files) GPIO controller.
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciIn Rockchip RK3328, the output only GPIO_MUTE pin, originally for codec mute
48c2ecf20Sopenharmony_cicontrol, can also be used for general purpose. It is manipulated by the
58c2ecf20Sopenharmony_ciGRF_SOC_CON10 register in GRF. Aside from the GPIO_MUTE pin, the HDMI pins can
68c2ecf20Sopenharmony_cialso be set in the same way.
78c2ecf20Sopenharmony_ci
88c2ecf20Sopenharmony_ciCurrently this GPIO controller only supports the mute pin. If needed in the
98c2ecf20Sopenharmony_cifuture, the HDMI pins support can also be added.
108c2ecf20Sopenharmony_ci
118c2ecf20Sopenharmony_ciRequired properties:
128c2ecf20Sopenharmony_ci- compatible: Should contain "rockchip,rk3328-grf-gpio".
138c2ecf20Sopenharmony_ci- gpio-controller: Marks the device node as a gpio controller.
148c2ecf20Sopenharmony_ci- #gpio-cells: Should be 2. The first cell is the pin number and
158c2ecf20Sopenharmony_ci  the second cell is used to specify the gpio polarity:
168c2ecf20Sopenharmony_ci    0 = Active high,
178c2ecf20Sopenharmony_ci    1 = Active low.
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ciExample:
208c2ecf20Sopenharmony_ci
218c2ecf20Sopenharmony_ci	grf: syscon@ff100000 {
228c2ecf20Sopenharmony_ci		compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
238c2ecf20Sopenharmony_ci
248c2ecf20Sopenharmony_ci		grf_gpio: grf-gpio {
258c2ecf20Sopenharmony_ci			compatible = "rockchip,rk3328-grf-gpio";
268c2ecf20Sopenharmony_ci			gpio-controller;
278c2ecf20Sopenharmony_ci			#gpio-cells = <2>;
288c2ecf20Sopenharmony_ci		};
298c2ecf20Sopenharmony_ci	};
308c2ecf20Sopenharmony_ci
318c2ecf20Sopenharmony_ciNote: The grf_gpio node should be declared as the child of the GRF (General
328c2ecf20Sopenharmony_ciRegister File) node. The GPIO_MUTE pin is referred to as <&grf_gpio 0>.
33