18c2ecf20Sopenharmony_ciMediatek MT7621 SoC GPIO controller bindings 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThe IP core used inside these SoCs has 3 banks of 32 GPIOs each. 48c2ecf20Sopenharmony_ciThe registers of all the banks are interwoven inside one single IO range. 58c2ecf20Sopenharmony_ciWe load one GPIO controller instance per bank. Also the GPIO controller can receive 68c2ecf20Sopenharmony_ciinterrupts on any of the GPIOs, either edge or level. It then interrupts the CPU 78c2ecf20Sopenharmony_ciusing GIC INT12. 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ciRequired properties for the top level node: 108c2ecf20Sopenharmony_ci- #gpio-cells : Should be two. The first cell is the GPIO pin number and the 118c2ecf20Sopenharmony_ci second cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. 128c2ecf20Sopenharmony_ci Only the GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported. 138c2ecf20Sopenharmony_ci- #interrupt-cells : Specifies the number of cells needed to encode an 148c2ecf20Sopenharmony_ci interrupt. Should be 2. The first cell defines the interrupt number, 158c2ecf20Sopenharmony_ci the second encodes the trigger flags encoded as described in 168c2ecf20Sopenharmony_ci Documentation/devicetree/bindings/interrupt-controller/interrupts.txt 178c2ecf20Sopenharmony_ci- compatible: 188c2ecf20Sopenharmony_ci - "mediatek,mt7621-gpio" for Mediatek controllers 198c2ecf20Sopenharmony_ci- reg : Physical base address and length of the controller's registers 208c2ecf20Sopenharmony_ci- interrupt-parent : phandle of the parent interrupt controller. 218c2ecf20Sopenharmony_ci- interrupts : Interrupt specifier for the controllers interrupt. 228c2ecf20Sopenharmony_ci- interrupt-controller : Mark the device node as an interrupt controller. 238c2ecf20Sopenharmony_ci- gpio-controller : Marks the device node as a GPIO controller. 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ciExample: 268c2ecf20Sopenharmony_ci gpio@600 { 278c2ecf20Sopenharmony_ci #gpio-cells = <2>; 288c2ecf20Sopenharmony_ci #interrupt-cells = <2>; 298c2ecf20Sopenharmony_ci compatible = "mediatek,mt7621-gpio"; 308c2ecf20Sopenharmony_ci gpio-controller; 318c2ecf20Sopenharmony_ci interrupt-controller; 328c2ecf20Sopenharmony_ci reg = <0x600 0x100>; 338c2ecf20Sopenharmony_ci interrupt-parent = <&gic>; 348c2ecf20Sopenharmony_ci interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>; 358c2ecf20Sopenharmony_ci }; 36