18c2ecf20Sopenharmony_ci* IBM/AMCC/APM GPIO Controller for PowerPC 4XX series and compatible SoCs 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciAll GPIOs are pin-shared with other functions. DCRs control whether a 48c2ecf20Sopenharmony_ciparticular pin that has GPIO capabilities acts as a GPIO or is used for 58c2ecf20Sopenharmony_cianother purpose. GPIO outputs are separately programmable to emulate 68c2ecf20Sopenharmony_cian open-drain driver. 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ciRequired properties: 98c2ecf20Sopenharmony_ci - compatible: must be "ibm,ppc4xx-gpio" 108c2ecf20Sopenharmony_ci - reg: address and length of the register set for the device 118c2ecf20Sopenharmony_ci - #gpio-cells: must be set to 2. The first cell is the pin number 128c2ecf20Sopenharmony_ci and the second cell is used to specify the gpio polarity: 138c2ecf20Sopenharmony_ci 0 = active high 148c2ecf20Sopenharmony_ci 1 = active low 158c2ecf20Sopenharmony_ci - gpio-controller: marks the device node as a gpio controller. 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ciExample: 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ciGPIO0: gpio@ef600b00 { 208c2ecf20Sopenharmony_ci compatible = "ibm,ppc4xx-gpio"; 218c2ecf20Sopenharmony_ci reg = <0xef600b00 0x00000048>; 228c2ecf20Sopenharmony_ci #gpio-cells = <2>; 238c2ecf20Sopenharmony_ci gpio-controller; 248c2ecf20Sopenharmony_ci}; 25