18c2ecf20Sopenharmony_ciBroadcom STB "UPG GIO" GPIO controller
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciThe controller's registers are organized as sets of eight 32-bit
48c2ecf20Sopenharmony_ciregisters with each set controlling a bank of up to 32 pins.  A single
58c2ecf20Sopenharmony_ciinterrupt is shared for all of the banks handled by the controller.
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_ciRequired properties:
88c2ecf20Sopenharmony_ci
98c2ecf20Sopenharmony_ci- compatible:
108c2ecf20Sopenharmony_ci    Must be "brcm,brcmstb-gpio"
118c2ecf20Sopenharmony_ci
128c2ecf20Sopenharmony_ci- reg:
138c2ecf20Sopenharmony_ci    Define the base and range of the I/O address space containing
148c2ecf20Sopenharmony_ci    the brcmstb GPIO controller registers
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_ci- #gpio-cells:
178c2ecf20Sopenharmony_ci    Should be <2>.  The first cell is the pin number (within the controller's
188c2ecf20Sopenharmony_ci    pin space), and the second is used for the following:
198c2ecf20Sopenharmony_ci    bit[0]: polarity (0 for active-high, 1 for active-low)
208c2ecf20Sopenharmony_ci
218c2ecf20Sopenharmony_ci- gpio-controller:
228c2ecf20Sopenharmony_ci    Specifies that the node is a GPIO controller.
238c2ecf20Sopenharmony_ci
248c2ecf20Sopenharmony_ci- brcm,gpio-bank-widths:
258c2ecf20Sopenharmony_ci    Number of GPIO lines for each bank.  Number of elements must
268c2ecf20Sopenharmony_ci    correspond to number of banks suggested by the 'reg' property.
278c2ecf20Sopenharmony_ci
288c2ecf20Sopenharmony_ciOptional properties:
298c2ecf20Sopenharmony_ci
308c2ecf20Sopenharmony_ci- interrupts:
318c2ecf20Sopenharmony_ci    The interrupt shared by all GPIO lines for this controller.
328c2ecf20Sopenharmony_ci
338c2ecf20Sopenharmony_ci- interrupts-extended:
348c2ecf20Sopenharmony_ci    Alternate form of specifying interrupts and parents that allows for
358c2ecf20Sopenharmony_ci    multiple parents.  This takes precedence over 'interrupts' and
368c2ecf20Sopenharmony_ci    'interrupt-parent'.  Wakeup-capable GPIO controllers often route their
378c2ecf20Sopenharmony_ci    wakeup interrupt lines through a different interrupt controller than the
388c2ecf20Sopenharmony_ci    primary interrupt line, making this property necessary.
398c2ecf20Sopenharmony_ci
408c2ecf20Sopenharmony_ci- #interrupt-cells:
418c2ecf20Sopenharmony_ci    Should be <2>.  The first cell is the GPIO number, the second should specify
428c2ecf20Sopenharmony_ci    flags.  The following subset of flags is supported:
438c2ecf20Sopenharmony_ci    - bits[3:0] trigger type and level flags
448c2ecf20Sopenharmony_ci        1 = low-to-high edge triggered
458c2ecf20Sopenharmony_ci        2 = high-to-low edge triggered
468c2ecf20Sopenharmony_ci        4 = active high level-sensitive
478c2ecf20Sopenharmony_ci        8 = active low level-sensitive
488c2ecf20Sopenharmony_ci      Valid combinations are 1, 2, 3, 4, 8.
498c2ecf20Sopenharmony_ci    See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
508c2ecf20Sopenharmony_ci
518c2ecf20Sopenharmony_ci- interrupt-controller:
528c2ecf20Sopenharmony_ci    Marks the device node as an interrupt controller
538c2ecf20Sopenharmony_ci
548c2ecf20Sopenharmony_ci- wakeup-source:
558c2ecf20Sopenharmony_ci    GPIOs for this controller can be used as a wakeup source
568c2ecf20Sopenharmony_ci
578c2ecf20Sopenharmony_ciExample:
588c2ecf20Sopenharmony_ci	upg_gio: gpio@f040a700 {
598c2ecf20Sopenharmony_ci		#gpio-cells = <2>;
608c2ecf20Sopenharmony_ci		#interrupt-cells = <2>;
618c2ecf20Sopenharmony_ci		compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
628c2ecf20Sopenharmony_ci		gpio-controller;
638c2ecf20Sopenharmony_ci		interrupt-controller;
648c2ecf20Sopenharmony_ci		reg = <0xf040a700 0x80>;
658c2ecf20Sopenharmony_ci		interrupt-parent = <&irq0_intc>;
668c2ecf20Sopenharmony_ci		interrupts = <0x6>;
678c2ecf20Sopenharmony_ci		brcm,gpio-bank-widths = <32 32 32 24>;
688c2ecf20Sopenharmony_ci	};
698c2ecf20Sopenharmony_ci
708c2ecf20Sopenharmony_ci	upg_gio_aon: gpio@f04172c0 {
718c2ecf20Sopenharmony_ci		#gpio-cells = <2>;
728c2ecf20Sopenharmony_ci		#interrupt-cells = <2>;
738c2ecf20Sopenharmony_ci		compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
748c2ecf20Sopenharmony_ci		gpio-controller;
758c2ecf20Sopenharmony_ci		interrupt-controller;
768c2ecf20Sopenharmony_ci		reg = <0xf04172c0 0x40>;
778c2ecf20Sopenharmony_ci		interrupt-parent = <&irq0_aon_intc>;
788c2ecf20Sopenharmony_ci		interrupts = <0x6>;
798c2ecf20Sopenharmony_ci		interrupts-extended = <&irq0_aon_intc 0x6>,
808c2ecf20Sopenharmony_ci			<&aon_pm_l2_intc 0x5>;
818c2ecf20Sopenharmony_ci		wakeup-source;
828c2ecf20Sopenharmony_ci		brcm,gpio-bank-widths = <18 4>;
838c2ecf20Sopenharmony_ci	};
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