18c2ecf20Sopenharmony_ci* NVIDIA Tegra APB DMA controller
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciRequired properties:
48c2ecf20Sopenharmony_ci- compatible: Should be "nvidia,<chip>-apbdma"
58c2ecf20Sopenharmony_ci- reg: Should contain DMA registers location and length. This shuld include
68c2ecf20Sopenharmony_ci  all of the per-channel registers.
78c2ecf20Sopenharmony_ci- interrupts: Should contain all of the per-channel DMA interrupts.
88c2ecf20Sopenharmony_ci- clocks: Must contain one entry, for the module clock.
98c2ecf20Sopenharmony_ci  See ../clocks/clock-bindings.txt for details.
108c2ecf20Sopenharmony_ci- resets : Must contain an entry for each entry in reset-names.
118c2ecf20Sopenharmony_ci  See ../reset/reset.txt for details.
128c2ecf20Sopenharmony_ci- reset-names : Must include the following entries:
138c2ecf20Sopenharmony_ci  - dma
148c2ecf20Sopenharmony_ci- #dma-cells : Must be <1>. This dictates the length of DMA specifiers in
158c2ecf20Sopenharmony_ci  client nodes' dmas properties. The specifier represents the DMA request
168c2ecf20Sopenharmony_ci  select value for the peripheral. For more details, consult the Tegra TRM's
178c2ecf20Sopenharmony_ci  documentation of the APB DMA channel control register REQ_SEL field.
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ciExamples:
208c2ecf20Sopenharmony_ci
218c2ecf20Sopenharmony_ciapbdma: dma@6000a000 {
228c2ecf20Sopenharmony_ci	compatible = "nvidia,tegra20-apbdma";
238c2ecf20Sopenharmony_ci	reg = <0x6000a000 0x1200>;
248c2ecf20Sopenharmony_ci	interrupts = < 0 136 0x04
258c2ecf20Sopenharmony_ci		       0 137 0x04
268c2ecf20Sopenharmony_ci		       0 138 0x04
278c2ecf20Sopenharmony_ci		       0 139 0x04
288c2ecf20Sopenharmony_ci		       0 140 0x04
298c2ecf20Sopenharmony_ci		       0 141 0x04
308c2ecf20Sopenharmony_ci		       0 142 0x04
318c2ecf20Sopenharmony_ci		       0 143 0x04
328c2ecf20Sopenharmony_ci		       0 144 0x04
338c2ecf20Sopenharmony_ci		       0 145 0x04
348c2ecf20Sopenharmony_ci		       0 146 0x04
358c2ecf20Sopenharmony_ci		       0 147 0x04
368c2ecf20Sopenharmony_ci		       0 148 0x04
378c2ecf20Sopenharmony_ci		       0 149 0x04
388c2ecf20Sopenharmony_ci		       0 150 0x04
398c2ecf20Sopenharmony_ci		       0 151 0x04 >;
408c2ecf20Sopenharmony_ci	clocks = <&tegra_car 34>;
418c2ecf20Sopenharmony_ci	resets = <&tegra_car 34>;
428c2ecf20Sopenharmony_ci	reset-names = "dma";
438c2ecf20Sopenharmony_ci	#dma-cells = <1>;
448c2ecf20Sopenharmony_ci};
45