18c2ecf20Sopenharmony_ci* Milbeaut AXI DMA Controller 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciMilbeaut AXI DMA controller has only memory to memory transfer capability. 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ci* DMA controller 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciRequired property: 88c2ecf20Sopenharmony_ci- compatible: Should be "socionext,milbeaut-m10v-xdmac" 98c2ecf20Sopenharmony_ci- reg: Should contain DMA registers location and length. 108c2ecf20Sopenharmony_ci- interrupts: Should contain all of the per-channel DMA interrupts. 118c2ecf20Sopenharmony_ci Number of channels is configurable - 2, 4 or 8, so 128c2ecf20Sopenharmony_ci the number of interrupts specified should be {2,4,8}. 138c2ecf20Sopenharmony_ci- #dma-cells: Should be 1. 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ciExample: 168c2ecf20Sopenharmony_ci xdmac0: dma-controller@1c250000 { 178c2ecf20Sopenharmony_ci compatible = "socionext,milbeaut-m10v-xdmac"; 188c2ecf20Sopenharmony_ci reg = <0x1c250000 0x1000>; 198c2ecf20Sopenharmony_ci interrupts = <0 17 0x4>, 208c2ecf20Sopenharmony_ci <0 18 0x4>, 218c2ecf20Sopenharmony_ci <0 19 0x4>, 228c2ecf20Sopenharmony_ci <0 20 0x4>; 238c2ecf20Sopenharmony_ci #dma-cells = <1>; 248c2ecf20Sopenharmony_ci }; 25