18c2ecf20Sopenharmony_ciTexas Instruments OMAP Display Subsystem
28c2ecf20Sopenharmony_ci========================================
38c2ecf20Sopenharmony_ci
48c2ecf20Sopenharmony_ciGeneric Description
58c2ecf20Sopenharmony_ci-------------------
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_ciThis document is a generic description of the OMAP Display Subsystem bindings.
88c2ecf20Sopenharmony_ciBinding details for each OMAP SoC version are described in respective binding
98c2ecf20Sopenharmony_cidocumentation.
108c2ecf20Sopenharmony_ci
118c2ecf20Sopenharmony_ciThe OMAP Display Subsystem (DSS) hardware consists of DSS Core, DISPC module and
128c2ecf20Sopenharmony_cia number of encoder modules. All DSS versions contain DSS Core and DISPC, but
138c2ecf20Sopenharmony_cithe encoder modules vary.
148c2ecf20Sopenharmony_ci
158c2ecf20Sopenharmony_ciThe DSS Core is the parent of the other DSS modules, and manages clock routing,
168c2ecf20Sopenharmony_ciintegration to the SoC, etc.
178c2ecf20Sopenharmony_ci
188c2ecf20Sopenharmony_ciDISPC is the display controller, which reads pixels from the memory and outputs
198c2ecf20Sopenharmony_cia RGB pixel stream to encoders.
208c2ecf20Sopenharmony_ci
218c2ecf20Sopenharmony_ciThe encoder modules encode the received RGB pixel stream to a video output like
228c2ecf20Sopenharmony_ciHDMI, MIPI DPI, etc.
238c2ecf20Sopenharmony_ci
248c2ecf20Sopenharmony_ciVideo Ports
258c2ecf20Sopenharmony_ci-----------
268c2ecf20Sopenharmony_ci
278c2ecf20Sopenharmony_ciThe DSS Core and the encoders have video port outputs. The structure of the
288c2ecf20Sopenharmony_civideo ports is described in Documentation/devicetree/bindings/graph.txt,
298c2ecf20Sopenharmony_ciand the properties for the ports and endpoints for each encoder are
308c2ecf20Sopenharmony_cidescribed in the SoC's DSS binding documentation.
318c2ecf20Sopenharmony_ci
328c2ecf20Sopenharmony_ciThe video ports are used to describe the connections to external hardware, like
338c2ecf20Sopenharmony_cipanels or external encoders.
348c2ecf20Sopenharmony_ci
358c2ecf20Sopenharmony_ciAliases
368c2ecf20Sopenharmony_ci-------
378c2ecf20Sopenharmony_ci
388c2ecf20Sopenharmony_ciThe board dts file may define aliases for displays to assign "displayX" style
398c2ecf20Sopenharmony_ciname for each display. If no aliases are defined, a semi-random number is used
408c2ecf20Sopenharmony_cifor the display.
418c2ecf20Sopenharmony_ci
428c2ecf20Sopenharmony_ciExample
438c2ecf20Sopenharmony_ci-------
448c2ecf20Sopenharmony_ci
458c2ecf20Sopenharmony_ciA shortened example of the DSS description for OMAP4, with non-relevant parts
468c2ecf20Sopenharmony_ciremoved, defined in omap4.dtsi:
478c2ecf20Sopenharmony_ci
488c2ecf20Sopenharmony_cidss: dss@58000000 {
498c2ecf20Sopenharmony_ci	compatible = "ti,omap4-dss";
508c2ecf20Sopenharmony_ci	reg = <0x58000000 0x80>;
518c2ecf20Sopenharmony_ci	status = "disabled";
528c2ecf20Sopenharmony_ci	ti,hwmods = "dss_core";
538c2ecf20Sopenharmony_ci	clocks = <&dss_dss_clk>;
548c2ecf20Sopenharmony_ci	clock-names = "fck";
558c2ecf20Sopenharmony_ci	#address-cells = <1>;
568c2ecf20Sopenharmony_ci	#size-cells = <1>;
578c2ecf20Sopenharmony_ci	ranges;
588c2ecf20Sopenharmony_ci
598c2ecf20Sopenharmony_ci	dispc@58001000 {
608c2ecf20Sopenharmony_ci		compatible = "ti,omap4-dispc";
618c2ecf20Sopenharmony_ci		reg = <0x58001000 0x1000>;
628c2ecf20Sopenharmony_ci		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
638c2ecf20Sopenharmony_ci		ti,hwmods = "dss_dispc";
648c2ecf20Sopenharmony_ci		clocks = <&dss_dss_clk>;
658c2ecf20Sopenharmony_ci		clock-names = "fck";
668c2ecf20Sopenharmony_ci	};
678c2ecf20Sopenharmony_ci
688c2ecf20Sopenharmony_ci	hdmi: encoder@58006000 {
698c2ecf20Sopenharmony_ci		compatible = "ti,omap4-hdmi";
708c2ecf20Sopenharmony_ci		reg = <0x58006000 0x200>,
718c2ecf20Sopenharmony_ci		      <0x58006200 0x100>,
728c2ecf20Sopenharmony_ci		      <0x58006300 0x100>,
738c2ecf20Sopenharmony_ci		      <0x58006400 0x1000>;
748c2ecf20Sopenharmony_ci		reg-names = "wp", "pll", "phy", "core";
758c2ecf20Sopenharmony_ci		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
768c2ecf20Sopenharmony_ci		status = "disabled";
778c2ecf20Sopenharmony_ci		ti,hwmods = "dss_hdmi";
788c2ecf20Sopenharmony_ci		clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
798c2ecf20Sopenharmony_ci		clock-names = "fck", "sys_clk";
808c2ecf20Sopenharmony_ci	};
818c2ecf20Sopenharmony_ci};
828c2ecf20Sopenharmony_ci
838c2ecf20Sopenharmony_ciA shortened example of the board description for OMAP4 Panda board, defined in
848c2ecf20Sopenharmony_ciomap4-panda.dts.
858c2ecf20Sopenharmony_ci
868c2ecf20Sopenharmony_ciThe Panda board has a DVI and a HDMI connector, and the board contains a TFP410
878c2ecf20Sopenharmony_cichip (MIPI DPI to DVI encoder) and a TPD12S015 chip (HDMI ESD protection & level
888c2ecf20Sopenharmony_cishifter). The video pipelines for the connectors are formed as follows:
898c2ecf20Sopenharmony_ci
908c2ecf20Sopenharmony_ciDSS Core --(MIPI DPI)--> TFP410 --(DVI)--> DVI Connector
918c2ecf20Sopenharmony_ciOMAP HDMI --(HDMI)--> TPD12S015 --(HDMI)--> HDMI Connector
928c2ecf20Sopenharmony_ci
938c2ecf20Sopenharmony_ci/ {
948c2ecf20Sopenharmony_ci	aliases {
958c2ecf20Sopenharmony_ci		display0 = &dvi0;
968c2ecf20Sopenharmony_ci		display1 = &hdmi0;
978c2ecf20Sopenharmony_ci	};
988c2ecf20Sopenharmony_ci
998c2ecf20Sopenharmony_ci	tfp410: encoder@0 {
1008c2ecf20Sopenharmony_ci		compatible = "ti,tfp410";
1018c2ecf20Sopenharmony_ci		gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;	/* 0, power-down */
1028c2ecf20Sopenharmony_ci
1038c2ecf20Sopenharmony_ci		pinctrl-names = "default";
1048c2ecf20Sopenharmony_ci		pinctrl-0 = <&tfp410_pins>;
1058c2ecf20Sopenharmony_ci
1068c2ecf20Sopenharmony_ci		ports {
1078c2ecf20Sopenharmony_ci			#address-cells = <1>;
1088c2ecf20Sopenharmony_ci			#size-cells = <0>;
1098c2ecf20Sopenharmony_ci
1108c2ecf20Sopenharmony_ci			port@0 {
1118c2ecf20Sopenharmony_ci				reg = <0>;
1128c2ecf20Sopenharmony_ci
1138c2ecf20Sopenharmony_ci				tfp410_in: endpoint@0 {
1148c2ecf20Sopenharmony_ci					remote-endpoint = <&dpi_out>;
1158c2ecf20Sopenharmony_ci				};
1168c2ecf20Sopenharmony_ci			};
1178c2ecf20Sopenharmony_ci
1188c2ecf20Sopenharmony_ci			port@1 {
1198c2ecf20Sopenharmony_ci				reg = <1>;
1208c2ecf20Sopenharmony_ci
1218c2ecf20Sopenharmony_ci				tfp410_out: endpoint@0 {
1228c2ecf20Sopenharmony_ci					remote-endpoint = <&dvi_connector_in>;
1238c2ecf20Sopenharmony_ci				};
1248c2ecf20Sopenharmony_ci			};
1258c2ecf20Sopenharmony_ci		};
1268c2ecf20Sopenharmony_ci	};
1278c2ecf20Sopenharmony_ci
1288c2ecf20Sopenharmony_ci	dvi0: connector@0 {
1298c2ecf20Sopenharmony_ci		compatible = "dvi-connector";
1308c2ecf20Sopenharmony_ci		label = "dvi";
1318c2ecf20Sopenharmony_ci
1328c2ecf20Sopenharmony_ci		i2c-bus = <&i2c3>;
1338c2ecf20Sopenharmony_ci
1348c2ecf20Sopenharmony_ci		port {
1358c2ecf20Sopenharmony_ci			dvi_connector_in: endpoint {
1368c2ecf20Sopenharmony_ci				remote-endpoint = <&tfp410_out>;
1378c2ecf20Sopenharmony_ci			};
1388c2ecf20Sopenharmony_ci		};
1398c2ecf20Sopenharmony_ci	};
1408c2ecf20Sopenharmony_ci
1418c2ecf20Sopenharmony_ci	tpd12s015: encoder@1 {
1428c2ecf20Sopenharmony_ci		compatible = "ti,tpd12s015";
1438c2ecf20Sopenharmony_ci
1448c2ecf20Sopenharmony_ci		pinctrl-names = "default";
1458c2ecf20Sopenharmony_ci		pinctrl-0 = <&tpd12s015_pins>;
1468c2ecf20Sopenharmony_ci
1478c2ecf20Sopenharmony_ci		gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>,	/* 60, CT CP HPD */
1488c2ecf20Sopenharmony_ci			<&gpio2 9 GPIO_ACTIVE_HIGH>,	/* 41, LS OE */
1498c2ecf20Sopenharmony_ci			<&gpio2 31 GPIO_ACTIVE_HIGH>;	/* 63, HPD */
1508c2ecf20Sopenharmony_ci
1518c2ecf20Sopenharmony_ci		ports {
1528c2ecf20Sopenharmony_ci			#address-cells = <1>;
1538c2ecf20Sopenharmony_ci			#size-cells = <0>;
1548c2ecf20Sopenharmony_ci
1558c2ecf20Sopenharmony_ci			port@0 {
1568c2ecf20Sopenharmony_ci				reg = <0>;
1578c2ecf20Sopenharmony_ci
1588c2ecf20Sopenharmony_ci				tpd12s015_in: endpoint@0 {
1598c2ecf20Sopenharmony_ci					remote-endpoint = <&hdmi_out>;
1608c2ecf20Sopenharmony_ci				};
1618c2ecf20Sopenharmony_ci			};
1628c2ecf20Sopenharmony_ci
1638c2ecf20Sopenharmony_ci			port@1 {
1648c2ecf20Sopenharmony_ci				reg = <1>;
1658c2ecf20Sopenharmony_ci
1668c2ecf20Sopenharmony_ci				tpd12s015_out: endpoint@0 {
1678c2ecf20Sopenharmony_ci					remote-endpoint = <&hdmi_connector_in>;
1688c2ecf20Sopenharmony_ci				};
1698c2ecf20Sopenharmony_ci			};
1708c2ecf20Sopenharmony_ci		};
1718c2ecf20Sopenharmony_ci	};
1728c2ecf20Sopenharmony_ci
1738c2ecf20Sopenharmony_ci	hdmi0: connector@1 {
1748c2ecf20Sopenharmony_ci		compatible = "hdmi-connector";
1758c2ecf20Sopenharmony_ci		label = "hdmi";
1768c2ecf20Sopenharmony_ci
1778c2ecf20Sopenharmony_ci		port {
1788c2ecf20Sopenharmony_ci			hdmi_connector_in: endpoint {
1798c2ecf20Sopenharmony_ci				remote-endpoint = <&tpd12s015_out>;
1808c2ecf20Sopenharmony_ci			};
1818c2ecf20Sopenharmony_ci		};
1828c2ecf20Sopenharmony_ci	};
1838c2ecf20Sopenharmony_ci};
1848c2ecf20Sopenharmony_ci
1858c2ecf20Sopenharmony_ci&dss {
1868c2ecf20Sopenharmony_ci	status = "ok";
1878c2ecf20Sopenharmony_ci
1888c2ecf20Sopenharmony_ci	pinctrl-names = "default";
1898c2ecf20Sopenharmony_ci	pinctrl-0 = <&dss_dpi_pins>;
1908c2ecf20Sopenharmony_ci
1918c2ecf20Sopenharmony_ci	port {
1928c2ecf20Sopenharmony_ci		dpi_out: endpoint {
1938c2ecf20Sopenharmony_ci			remote-endpoint = <&tfp410_in>;
1948c2ecf20Sopenharmony_ci			data-lines = <24>;
1958c2ecf20Sopenharmony_ci		};
1968c2ecf20Sopenharmony_ci	};
1978c2ecf20Sopenharmony_ci};
1988c2ecf20Sopenharmony_ci
1998c2ecf20Sopenharmony_ci&hdmi {
2008c2ecf20Sopenharmony_ci	status = "ok";
2018c2ecf20Sopenharmony_ci	vdda-supply = <&vdac>;
2028c2ecf20Sopenharmony_ci
2038c2ecf20Sopenharmony_ci	pinctrl-names = "default";
2048c2ecf20Sopenharmony_ci	pinctrl-0 = <&dss_hdmi_pins>;
2058c2ecf20Sopenharmony_ci
2068c2ecf20Sopenharmony_ci	port {
2078c2ecf20Sopenharmony_ci		hdmi_out: endpoint {
2088c2ecf20Sopenharmony_ci			remote-endpoint = <&tpd12s015_in>;
2098c2ecf20Sopenharmony_ci		};
2108c2ecf20Sopenharmony_ci	};
2118c2ecf20Sopenharmony_ci};
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