18c2ecf20Sopenharmony_ciTexas Instruments DRA7x Display Subsystem
28c2ecf20Sopenharmony_ci=========================================
38c2ecf20Sopenharmony_ci
48c2ecf20Sopenharmony_ciSee Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
58c2ecf20Sopenharmony_cidescription about OMAP Display Subsystem bindings.
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_ciDSS Core
88c2ecf20Sopenharmony_ci--------
98c2ecf20Sopenharmony_ci
108c2ecf20Sopenharmony_ciRequired properties:
118c2ecf20Sopenharmony_ci- compatible: "ti,dra7-dss"
128c2ecf20Sopenharmony_ci- reg: address and length of the register spaces for 'dss'
138c2ecf20Sopenharmony_ci- ti,hwmods: "dss_core"
148c2ecf20Sopenharmony_ci- clocks: handle to fclk
158c2ecf20Sopenharmony_ci- clock-names: "fck"
168c2ecf20Sopenharmony_ci- syscon: phandle to control module core syscon node
178c2ecf20Sopenharmony_ci
188c2ecf20Sopenharmony_ciOptional properties:
198c2ecf20Sopenharmony_ci
208c2ecf20Sopenharmony_ciSome DRA7xx SoCs have one dedicated video PLL, some have two. These properties
218c2ecf20Sopenharmony_cican be used to describe the video PLLs:
228c2ecf20Sopenharmony_ci
238c2ecf20Sopenharmony_ci- reg: address and length of the register spaces for 'pll1_clkctrl',
248c2ecf20Sopenharmony_ci  'pll1', 'pll2_clkctrl', 'pll2'
258c2ecf20Sopenharmony_ci- clocks: handle to video1 pll clock and video2 pll clock
268c2ecf20Sopenharmony_ci- clock-names: "video1_clk" and "video2_clk"
278c2ecf20Sopenharmony_ci
288c2ecf20Sopenharmony_ciRequired nodes:
298c2ecf20Sopenharmony_ci- DISPC
308c2ecf20Sopenharmony_ci
318c2ecf20Sopenharmony_ciOptional nodes:
328c2ecf20Sopenharmony_ci- DSS Submodules: HDMI
338c2ecf20Sopenharmony_ci- Video port for DPI output
348c2ecf20Sopenharmony_ci
358c2ecf20Sopenharmony_ciDPI Endpoint required properties:
368c2ecf20Sopenharmony_ci- data-lines: number of lines used
378c2ecf20Sopenharmony_ci
388c2ecf20Sopenharmony_ci
398c2ecf20Sopenharmony_ciDISPC
408c2ecf20Sopenharmony_ci-----
418c2ecf20Sopenharmony_ci
428c2ecf20Sopenharmony_ciRequired properties:
438c2ecf20Sopenharmony_ci- compatible: "ti,dra7-dispc"
448c2ecf20Sopenharmony_ci- reg: address and length of the register space
458c2ecf20Sopenharmony_ci- ti,hwmods: "dss_dispc"
468c2ecf20Sopenharmony_ci- interrupts: the DISPC interrupt
478c2ecf20Sopenharmony_ci- clocks: handle to fclk
488c2ecf20Sopenharmony_ci- clock-names: "fck"
498c2ecf20Sopenharmony_ci
508c2ecf20Sopenharmony_ciOptional properties:
518c2ecf20Sopenharmony_ci- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
528c2ecf20Sopenharmony_ci			in bytes per second
538c2ecf20Sopenharmony_ci
548c2ecf20Sopenharmony_ci
558c2ecf20Sopenharmony_ciHDMI
568c2ecf20Sopenharmony_ci----
578c2ecf20Sopenharmony_ci
588c2ecf20Sopenharmony_ciRequired properties:
598c2ecf20Sopenharmony_ci- compatible: "ti,dra7-hdmi"
608c2ecf20Sopenharmony_ci- reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy',
618c2ecf20Sopenharmony_ci       'core'
628c2ecf20Sopenharmony_ci- reg-names: "wp", "pll", "phy", "core"
638c2ecf20Sopenharmony_ci- interrupts: the HDMI interrupt line
648c2ecf20Sopenharmony_ci- ti,hwmods: "dss_hdmi"
658c2ecf20Sopenharmony_ci- vdda-supply: vdda power supply
668c2ecf20Sopenharmony_ci- clocks: handles to fclk and pll clock
678c2ecf20Sopenharmony_ci- clock-names: "fck", "sys_clk"
688c2ecf20Sopenharmony_ci
698c2ecf20Sopenharmony_ciOptional nodes:
708c2ecf20Sopenharmony_ci- Video port for HDMI output
718c2ecf20Sopenharmony_ci
728c2ecf20Sopenharmony_ciHDMI Endpoint optional properties:
738c2ecf20Sopenharmony_ci- lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
748c2ecf20Sopenharmony_ci  D1+, D1-, D2+, D2-. (default: 0,1,2,3,4,5,6,7)
75