18c2ecf20Sopenharmony_ciNVIDIA Tegra MIPI pad calibration controller
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciRequired properties:
48c2ecf20Sopenharmony_ci- compatible: "nvidia,tegra<chip>-mipi"
58c2ecf20Sopenharmony_ci- reg: Physical base address and length of the controller's registers.
68c2ecf20Sopenharmony_ci- clocks: Must contain an entry for each entry in clock-names.
78c2ecf20Sopenharmony_ci  See ../clocks/clock-bindings.txt for details.
88c2ecf20Sopenharmony_ci- clock-names: Must include the following entries:
98c2ecf20Sopenharmony_ci  - mipi-cal
108c2ecf20Sopenharmony_ci- #nvidia,mipi-calibrate-cells: Should be 1. The cell is a bitmask of the pads
118c2ecf20Sopenharmony_ci  that need to be calibrated for a given device.
128c2ecf20Sopenharmony_ci
138c2ecf20Sopenharmony_ciUser nodes need to contain an nvidia,mipi-calibrate property that has a
148c2ecf20Sopenharmony_ciphandle to refer to the calibration controller node and a bitmask of the pads
158c2ecf20Sopenharmony_cithat need to be calibrated.
168c2ecf20Sopenharmony_ci
178c2ecf20Sopenharmony_ciExample:
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ci	mipi: mipi@700e3000 {
208c2ecf20Sopenharmony_ci		compatible = "nvidia,tegra114-mipi";
218c2ecf20Sopenharmony_ci		reg = <0x700e3000 0x100>;
228c2ecf20Sopenharmony_ci		clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
238c2ecf20Sopenharmony_ci		clock-names = "mipi-cal";
248c2ecf20Sopenharmony_ci		#nvidia,mipi-calibrate-cells = <1>;
258c2ecf20Sopenharmony_ci	};
268c2ecf20Sopenharmony_ci
278c2ecf20Sopenharmony_ci	...
288c2ecf20Sopenharmony_ci
298c2ecf20Sopenharmony_ci	host1x@50000000 {
308c2ecf20Sopenharmony_ci		...
318c2ecf20Sopenharmony_ci
328c2ecf20Sopenharmony_ci		dsi@54300000 {
338c2ecf20Sopenharmony_ci			...
348c2ecf20Sopenharmony_ci
358c2ecf20Sopenharmony_ci			nvidia,mipi-calibrate = <&mipi 0x060>;
368c2ecf20Sopenharmony_ci
378c2ecf20Sopenharmony_ci			...
388c2ecf20Sopenharmony_ci		};
398c2ecf20Sopenharmony_ci
408c2ecf20Sopenharmony_ci		...
418c2ecf20Sopenharmony_ci	};
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