18c2ecf20Sopenharmony_ciST-Ericsson Multi Channel Display Engine MCDE
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciThe ST-Ericsson MCDE is a display controller with support for compositing
48c2ecf20Sopenharmony_ciand displaying several channels memory resident graphics data on DSI or
58c2ecf20Sopenharmony_ciLCD displays or bridges. It is used in the ST-Ericsson U8500 platform.
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_ciRequired properties:
88c2ecf20Sopenharmony_ci
98c2ecf20Sopenharmony_ci- compatible: must be:
108c2ecf20Sopenharmony_ci  "ste,mcde"
118c2ecf20Sopenharmony_ci- reg: register base for the main MCDE control registers, should be
128c2ecf20Sopenharmony_ci  0x1000 in size
138c2ecf20Sopenharmony_ci- interrupts: the interrupt line for the MCDE
148c2ecf20Sopenharmony_ci- epod-supply: a phandle to the EPOD regulator
158c2ecf20Sopenharmony_ci- vana-supply: a phandle to the analog voltage regulator
168c2ecf20Sopenharmony_ci- clocks: an array of the MCDE clocks in this strict order:
178c2ecf20Sopenharmony_ci  MCDECLK (main MCDE clock), LCDCLK (LCD clock), PLLDSI
188c2ecf20Sopenharmony_ci  (HDMI clock), DSI0ESCLK (DSI0 energy save clock),
198c2ecf20Sopenharmony_ci  DSI1ESCLK (DSI1 energy save clock), DSI2ESCLK (DSI2 energy
208c2ecf20Sopenharmony_ci  save clock)
218c2ecf20Sopenharmony_ci- clock-names: must be the following array:
228c2ecf20Sopenharmony_ci  "mcde", "lcd", "hdmi"
238c2ecf20Sopenharmony_ci  to match the required clock inputs above.
248c2ecf20Sopenharmony_ci- #address-cells: should be <1> (for the DSI hosts that will be children)
258c2ecf20Sopenharmony_ci- #size-cells: should be <1> (for the DSI hosts that will be children)
268c2ecf20Sopenharmony_ci- ranges: this should always be stated
278c2ecf20Sopenharmony_ci
288c2ecf20Sopenharmony_ciRequired subnodes:
298c2ecf20Sopenharmony_ci
308c2ecf20Sopenharmony_ciThe devicetree must specify subnodes for the DSI host adapters.
318c2ecf20Sopenharmony_ciThese must have the following characteristics:
328c2ecf20Sopenharmony_ci
338c2ecf20Sopenharmony_ci- compatible: must be:
348c2ecf20Sopenharmony_ci  "ste,mcde-dsi"
358c2ecf20Sopenharmony_ci- reg: must specify the register range for the DSI host
368c2ecf20Sopenharmony_ci- vana-supply: phandle to the VANA voltage regulator
378c2ecf20Sopenharmony_ci- clocks: phandles to the high speed and low power (energy save) clocks
388c2ecf20Sopenharmony_ci  the high speed clock is not present on the third (dsi2) block, so it
398c2ecf20Sopenharmony_ci  should only have the "lp" clock
408c2ecf20Sopenharmony_ci- clock-names: "hs" for the high speed clock and "lp" for the low power
418c2ecf20Sopenharmony_ci  (energy save) clock
428c2ecf20Sopenharmony_ci- #address-cells: should be <1>
438c2ecf20Sopenharmony_ci- #size-cells: should be <0>
448c2ecf20Sopenharmony_ci
458c2ecf20Sopenharmony_ciDisplay panels and bridges will appear as children on the DSI hosts, and
468c2ecf20Sopenharmony_cithe displays are connected to the DSI hosts using the common binding
478c2ecf20Sopenharmony_cifor video transmitter interfaces; see
488c2ecf20Sopenharmony_ciDocumentation/devicetree/bindings/media/video-interfaces.txt
498c2ecf20Sopenharmony_ci
508c2ecf20Sopenharmony_ciIf a DSI host is unused (not connected) it will have no children defined.
518c2ecf20Sopenharmony_ci
528c2ecf20Sopenharmony_ciExample:
538c2ecf20Sopenharmony_ci
548c2ecf20Sopenharmony_cimcde@a0350000 {
558c2ecf20Sopenharmony_ci	compatible = "ste,mcde";
568c2ecf20Sopenharmony_ci	reg = <0xa0350000 0x1000>;
578c2ecf20Sopenharmony_ci	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
588c2ecf20Sopenharmony_ci	epod-supply = <&db8500_b2r2_mcde_reg>;
598c2ecf20Sopenharmony_ci	vana-supply = <&ab8500_ldo_ana_reg>;
608c2ecf20Sopenharmony_ci	clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
618c2ecf20Sopenharmony_ci		 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
628c2ecf20Sopenharmony_ci		 <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */
638c2ecf20Sopenharmony_ci	clock-names = "mcde", "lcd", "hdmi";
648c2ecf20Sopenharmony_ci	#address-cells = <1>;
658c2ecf20Sopenharmony_ci	#size-cells = <1>;
668c2ecf20Sopenharmony_ci	ranges;
678c2ecf20Sopenharmony_ci
688c2ecf20Sopenharmony_ci	dsi0: dsi@a0351000 {
698c2ecf20Sopenharmony_ci		compatible = "ste,mcde-dsi";
708c2ecf20Sopenharmony_ci		reg = <0xa0351000 0x1000>;
718c2ecf20Sopenharmony_ci		vana-supply = <&ab8500_ldo_ana_reg>;
728c2ecf20Sopenharmony_ci		clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>;
738c2ecf20Sopenharmony_ci		clock-names = "hs", "lp";
748c2ecf20Sopenharmony_ci		#address-cells = <1>;
758c2ecf20Sopenharmony_ci		#size-cells = <0>;
768c2ecf20Sopenharmony_ci
778c2ecf20Sopenharmony_ci		panel {
788c2ecf20Sopenharmony_ci			compatible = "samsung,s6d16d0";
798c2ecf20Sopenharmony_ci			reg = <0>;
808c2ecf20Sopenharmony_ci			vdd1-supply = <&ab8500_ldo_aux1_reg>;
818c2ecf20Sopenharmony_ci			reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
828c2ecf20Sopenharmony_ci		};
838c2ecf20Sopenharmony_ci
848c2ecf20Sopenharmony_ci	};
858c2ecf20Sopenharmony_ci	dsi1: dsi@a0352000 {
868c2ecf20Sopenharmony_ci		compatible = "ste,mcde-dsi";
878c2ecf20Sopenharmony_ci		reg = <0xa0352000 0x1000>;
888c2ecf20Sopenharmony_ci		vana-supply = <&ab8500_ldo_ana_reg>;
898c2ecf20Sopenharmony_ci		clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>;
908c2ecf20Sopenharmony_ci		clock-names = "hs", "lp";
918c2ecf20Sopenharmony_ci		#address-cells = <1>;
928c2ecf20Sopenharmony_ci		#size-cells = <0>;
938c2ecf20Sopenharmony_ci	};
948c2ecf20Sopenharmony_ci	dsi2: dsi@a0353000 {
958c2ecf20Sopenharmony_ci		compatible = "ste,mcde-dsi";
968c2ecf20Sopenharmony_ci		reg = <0xa0353000 0x1000>;
978c2ecf20Sopenharmony_ci		vana-supply = <&ab8500_ldo_ana_reg>;
988c2ecf20Sopenharmony_ci		/* This DSI port only has the Low Power / Energy Save clock */
998c2ecf20Sopenharmony_ci		clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>;
1008c2ecf20Sopenharmony_ci		clock-names = "lp";
1018c2ecf20Sopenharmony_ci		#address-cells = <1>;
1028c2ecf20Sopenharmony_ci		#size-cells = <0>;
1038c2ecf20Sopenharmony_ci	};
1048c2ecf20Sopenharmony_ci};
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