18c2ecf20Sopenharmony_ciARC PGU
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciThis is a display controller found on several development boards produced
48c2ecf20Sopenharmony_ciby Synopsys. The ARC PGU is an RGB streamer that reads the data from a
58c2ecf20Sopenharmony_ciframebuffer and sends it to a single digital encoder (usually HDMI).
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_ciRequired properties:
88c2ecf20Sopenharmony_ci  - compatible: "snps,arcpgu"
98c2ecf20Sopenharmony_ci  - reg: Physical base address and length of the controller's registers.
108c2ecf20Sopenharmony_ci  - clocks: A list of phandle + clock-specifier pairs, one for each
118c2ecf20Sopenharmony_ci    entry in 'clock-names'.
128c2ecf20Sopenharmony_ci  - clock-names: A list of clock names. For ARC PGU it should contain:
138c2ecf20Sopenharmony_ci      - "pxlclk" for the clock feeding the output PLL of the controller.
148c2ecf20Sopenharmony_ci
158c2ecf20Sopenharmony_ciRequired sub-nodes:
168c2ecf20Sopenharmony_ci  - port: The PGU connection to an encoder chip.
178c2ecf20Sopenharmony_ci
188c2ecf20Sopenharmony_ciExample:
198c2ecf20Sopenharmony_ci
208c2ecf20Sopenharmony_ci/ {
218c2ecf20Sopenharmony_ci	...
228c2ecf20Sopenharmony_ci
238c2ecf20Sopenharmony_ci	pgu@XXXXXXXX {
248c2ecf20Sopenharmony_ci		compatible = "snps,arcpgu";
258c2ecf20Sopenharmony_ci		reg = <0xXXXXXXXX 0x400>;
268c2ecf20Sopenharmony_ci		clocks = <&clock_node>;
278c2ecf20Sopenharmony_ci		clock-names = "pxlclk";
288c2ecf20Sopenharmony_ci
298c2ecf20Sopenharmony_ci		port {
308c2ecf20Sopenharmony_ci			pgu_output: endpoint {
318c2ecf20Sopenharmony_ci				remote-endpoint = <&hdmi_enc_input>;
328c2ecf20Sopenharmony_ci			};
338c2ecf20Sopenharmony_ci		};
348c2ecf20Sopenharmony_ci	};
358c2ecf20Sopenharmony_ci};
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