18c2ecf20Sopenharmony_ciRockchip RK3399 specific extensions to the cdn Display Port 28c2ecf20Sopenharmony_ci================================ 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ciRequired properties: 58c2ecf20Sopenharmony_ci- compatible: must be "rockchip,rk3399-cdn-dp" 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ci- reg: physical base address of the controller and length 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci- clocks: from common clock binding: handle to dp clock. 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci- clock-names: from common clock binding: 128c2ecf20Sopenharmony_ci Required elements: "core-clk" "pclk" "spdif" "grf" 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci- resets : a list of phandle + reset specifier pairs 158c2ecf20Sopenharmony_ci- reset-names : string of reset names 168c2ecf20Sopenharmony_ci Required elements: "apb", "core", "dptx", "spdif" 178c2ecf20Sopenharmony_ci- power-domains : power-domain property defined with a phandle 188c2ecf20Sopenharmony_ci to respective power domain. 198c2ecf20Sopenharmony_ci- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE> 208c2ecf20Sopenharmony_ci- assigned-clock-rates : the DP core clk frequency, shall be: 100000000 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci- rockchip,grf: this soc should set GRF regs, so need get grf here. 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ci- ports: contain a port nodes with endpoint definitions as defined in 258c2ecf20Sopenharmony_ci Documentation/devicetree/bindings/media/video-interfaces.txt. 268c2ecf20Sopenharmony_ci contained 2 endpoints, connecting to the output of vop. 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_ci- phys: from general PHY binding: the phandle for the PHY device. 298c2ecf20Sopenharmony_ci 308c2ecf20Sopenharmony_ci- extcon: extcon specifier for the Power Delivery 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ci- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_ci------------------------------------------------------------------------------- 358c2ecf20Sopenharmony_ci 368c2ecf20Sopenharmony_ciExample: 378c2ecf20Sopenharmony_ci cdn_dp: dp@fec00000 { 388c2ecf20Sopenharmony_ci compatible = "rockchip,rk3399-cdn-dp"; 398c2ecf20Sopenharmony_ci reg = <0x0 0xfec00000 0x0 0x100000>; 408c2ecf20Sopenharmony_ci interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 418c2ecf20Sopenharmony_ci clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 428c2ecf20Sopenharmony_ci <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; 438c2ecf20Sopenharmony_ci clock-names = "core-clk", "pclk", "spdif", "grf"; 448c2ecf20Sopenharmony_ci assigned-clocks = <&cru SCLK_DP_CORE>; 458c2ecf20Sopenharmony_ci assigned-clock-rates = <100000000>; 468c2ecf20Sopenharmony_ci power-domains = <&power RK3399_PD_HDCP>; 478c2ecf20Sopenharmony_ci phys = <&tcphy0_dp>, <&tcphy1_dp>; 488c2ecf20Sopenharmony_ci resets = <&cru SRST_DPTX_SPDIF_REC>; 498c2ecf20Sopenharmony_ci reset-names = "spdif"; 508c2ecf20Sopenharmony_ci extcon = <&fusb0>, <&fusb1>; 518c2ecf20Sopenharmony_ci rockchip,grf = <&grf>; 528c2ecf20Sopenharmony_ci #address-cells = <1>; 538c2ecf20Sopenharmony_ci #size-cells = <0>; 548c2ecf20Sopenharmony_ci #sound-dai-cells = <1>; 558c2ecf20Sopenharmony_ci 568c2ecf20Sopenharmony_ci ports { 578c2ecf20Sopenharmony_ci #address-cells = <1>; 588c2ecf20Sopenharmony_ci #size-cells = <0>; 598c2ecf20Sopenharmony_ci 608c2ecf20Sopenharmony_ci dp_in: port { 618c2ecf20Sopenharmony_ci #address-cells = <1>; 628c2ecf20Sopenharmony_ci #size-cells = <0>; 638c2ecf20Sopenharmony_ci dp_in_vopb: endpoint@0 { 648c2ecf20Sopenharmony_ci reg = <0>; 658c2ecf20Sopenharmony_ci remote-endpoint = <&vopb_out_dp>; 668c2ecf20Sopenharmony_ci }; 678c2ecf20Sopenharmony_ci 688c2ecf20Sopenharmony_ci dp_in_vopl: endpoint@1 { 698c2ecf20Sopenharmony_ci reg = <1>; 708c2ecf20Sopenharmony_ci remote-endpoint = <&vopl_out_dp>; 718c2ecf20Sopenharmony_ci }; 728c2ecf20Sopenharmony_ci }; 738c2ecf20Sopenharmony_ci }; 748c2ecf20Sopenharmony_ci }; 75