18c2ecf20Sopenharmony_ciDevice Tree bindings for Freescale DCU DRM Driver
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciRequired properties:
48c2ecf20Sopenharmony_ci- compatible:		Should be one of
58c2ecf20Sopenharmony_ci	* "fsl,ls1021a-dcu".
68c2ecf20Sopenharmony_ci	* "fsl,vf610-dcu".
78c2ecf20Sopenharmony_ci
88c2ecf20Sopenharmony_ci- reg:			Address and length of the register set for dcu.
98c2ecf20Sopenharmony_ci- clocks:		Handle to "dcu" and "pix" clock (in the order below)
108c2ecf20Sopenharmony_ci			This can be the same clock (e.g. LS1021a)
118c2ecf20Sopenharmony_ci			See ../clocks/clock-bindings.txt for details.
128c2ecf20Sopenharmony_ci- clock-names:		Should be "dcu" and "pix"
138c2ecf20Sopenharmony_ci			See ../clocks/clock-bindings.txt for details.
148c2ecf20Sopenharmony_ci- big-endian		Boolean property, LS1021A DCU registers are big-endian.
158c2ecf20Sopenharmony_ci- port			Video port for the panel output
168c2ecf20Sopenharmony_ci
178c2ecf20Sopenharmony_ciOptional properties:
188c2ecf20Sopenharmony_ci- fsl,tcon:		The phandle to the timing controller node.
198c2ecf20Sopenharmony_ci
208c2ecf20Sopenharmony_ciExamples:
218c2ecf20Sopenharmony_cidcu: dcu@2ce0000 {
228c2ecf20Sopenharmony_ci	compatible = "fsl,ls1021a-dcu";
238c2ecf20Sopenharmony_ci	reg = <0x0 0x2ce0000 0x0 0x10000>;
248c2ecf20Sopenharmony_ci	clocks = <&platform_clk 0>, <&platform_clk 0>;
258c2ecf20Sopenharmony_ci	clock-names = "dcu", "pix";
268c2ecf20Sopenharmony_ci	big-endian;
278c2ecf20Sopenharmony_ci	fsl,tcon = <&tcon>;
288c2ecf20Sopenharmony_ci
298c2ecf20Sopenharmony_ci	port {
308c2ecf20Sopenharmony_ci		dcu_out: endpoint {
318c2ecf20Sopenharmony_ci			remote-endpoint = <&panel_out>;
328c2ecf20Sopenharmony_ci	     };
338c2ecf20Sopenharmony_ci	};
348c2ecf20Sopenharmony_ci};
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