18c2ecf20Sopenharmony_ciDevice-Tree bindings for Samsung SoC display controller (FIMD) 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciFIMD (Fully Interactive Mobile Display) is the Display Controller for the 48c2ecf20Sopenharmony_ciSamsung series of SoCs which transfers the image data from a video memory 58c2ecf20Sopenharmony_cibuffer to an external LCD interface. 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciRequired properties: 88c2ecf20Sopenharmony_ci- compatible: value should be one of the following 98c2ecf20Sopenharmony_ci "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */ 108c2ecf20Sopenharmony_ci "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */ 118c2ecf20Sopenharmony_ci "samsung,s5pv210-fimd"; /* for S5PV210 SoC */ 128c2ecf20Sopenharmony_ci "samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */ 138c2ecf20Sopenharmony_ci "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */ 148c2ecf20Sopenharmony_ci "samsung,exynos5250-fimd"; /* for Exynos5250 SoCs */ 158c2ecf20Sopenharmony_ci "samsung,exynos5420-fimd"; /* for Exynos5420/5422/5800 SoCs */ 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci- reg: physical base address and length of the FIMD registers set. 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ci- interrupts: should contain a list of all FIMD IP block interrupts in the 208c2ecf20Sopenharmony_ci order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier 218c2ecf20Sopenharmony_ci format depends on the interrupt controller used. 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci- interrupt-names: should contain the interrupt names: "fifo", "vsync", 248c2ecf20Sopenharmony_ci "lcd_sys", in the same order as they were listed in the interrupts 258c2ecf20Sopenharmony_ci property. 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ci- pinctrl-0: pin control group to be used for this controller. 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ci- pinctrl-names: must contain a "default" entry. 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ci- clocks: must include clock specifiers corresponding to entries in the 328c2ecf20Sopenharmony_ci clock-names property. 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_ci- clock-names: list of clock names sorted in the same order as the clocks 358c2ecf20Sopenharmony_ci property. Must contain "sclk_fimd" and "fimd". 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_ciOptional Properties: 388c2ecf20Sopenharmony_ci- power-domains: a phandle to FIMD power domain node. 398c2ecf20Sopenharmony_ci- samsung,invert-vden: video enable signal is inverted 408c2ecf20Sopenharmony_ci- samsung,invert-vclk: video clock signal is inverted 418c2ecf20Sopenharmony_ci- display-timings: timing settings for FIMD, as described in document [1]. 428c2ecf20Sopenharmony_ci Can be used in case timings cannot be provided otherwise 438c2ecf20Sopenharmony_ci or to override timings provided by the panel. 448c2ecf20Sopenharmony_ci- samsung,sysreg: handle to syscon used to control the system registers 458c2ecf20Sopenharmony_ci- i80-if-timings: timing configuration for lcd i80 interface support. 468c2ecf20Sopenharmony_ci - cs-setup: clock cycles for the active period of address signal is enabled 478c2ecf20Sopenharmony_ci until chip select is enabled. 488c2ecf20Sopenharmony_ci If not specified, the default value(0) will be used. 498c2ecf20Sopenharmony_ci - wr-setup: clock cycles for the active period of CS signal is enabled until 508c2ecf20Sopenharmony_ci write signal is enabled. 518c2ecf20Sopenharmony_ci If not specified, the default value(0) will be used. 528c2ecf20Sopenharmony_ci - wr-active: clock cycles for the active period of CS is enabled. 538c2ecf20Sopenharmony_ci If not specified, the default value(1) will be used. 548c2ecf20Sopenharmony_ci - wr-hold: clock cycles for the active period of CS is disabled until write 558c2ecf20Sopenharmony_ci signal is disabled. 568c2ecf20Sopenharmony_ci If not specified, the default value(0) will be used. 578c2ecf20Sopenharmony_ci 588c2ecf20Sopenharmony_ci The parameters are defined as: 598c2ecf20Sopenharmony_ci 608c2ecf20Sopenharmony_ci VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|?? 618c2ecf20Sopenharmony_ci : : : : : 628c2ecf20Sopenharmony_ci Address Output --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX 638c2ecf20Sopenharmony_ci | cs-setup+1 | : : : 648c2ecf20Sopenharmony_ci |<---------->| : : : 658c2ecf20Sopenharmony_ci Chip Select ???????????????|____________:____________:____________|?? 668c2ecf20Sopenharmony_ci | wr-setup+1 | | wr-hold+1 | 678c2ecf20Sopenharmony_ci |<---------->| |<---------->| 688c2ecf20Sopenharmony_ci Write Enable ????????????????????????????|____________|??????????????? 698c2ecf20Sopenharmony_ci | wr-active+1| 708c2ecf20Sopenharmony_ci |<---------->| 718c2ecf20Sopenharmony_ci Video Data ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>-- 728c2ecf20Sopenharmony_ci 738c2ecf20Sopenharmony_ciThe device node can contain 'port' child nodes according to the bindings defined 748c2ecf20Sopenharmony_ciin [2]. The following are properties specific to those nodes: 758c2ecf20Sopenharmony_ci- reg: (required) port index, can be: 768c2ecf20Sopenharmony_ci 0 - for CAMIF0 input, 778c2ecf20Sopenharmony_ci 1 - for CAMIF1 input, 788c2ecf20Sopenharmony_ci 2 - for CAMIF2 input, 798c2ecf20Sopenharmony_ci 3 - for parallel output, 808c2ecf20Sopenharmony_ci 4 - for write-back interface 818c2ecf20Sopenharmony_ci 828c2ecf20Sopenharmony_ci[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt 838c2ecf20Sopenharmony_ci[2]: Documentation/devicetree/bindings/media/video-interfaces.txt 848c2ecf20Sopenharmony_ci 858c2ecf20Sopenharmony_ciExample: 868c2ecf20Sopenharmony_ci 878c2ecf20Sopenharmony_ciSoC specific DT entry: 888c2ecf20Sopenharmony_ci 898c2ecf20Sopenharmony_ci fimd@11c00000 { 908c2ecf20Sopenharmony_ci compatible = "samsung,exynos4210-fimd"; 918c2ecf20Sopenharmony_ci interrupt-parent = <&combiner>; 928c2ecf20Sopenharmony_ci reg = <0x11c00000 0x20000>; 938c2ecf20Sopenharmony_ci interrupt-names = "fifo", "vsync", "lcd_sys"; 948c2ecf20Sopenharmony_ci interrupts = <11 0>, <11 1>, <11 2>; 958c2ecf20Sopenharmony_ci clocks = <&clock 140>, <&clock 283>; 968c2ecf20Sopenharmony_ci clock-names = "sclk_fimd", "fimd"; 978c2ecf20Sopenharmony_ci power-domains = <&pd_lcd0>; 988c2ecf20Sopenharmony_ci status = "disabled"; 998c2ecf20Sopenharmony_ci }; 1008c2ecf20Sopenharmony_ci 1018c2ecf20Sopenharmony_ciBoard specific DT entry: 1028c2ecf20Sopenharmony_ci 1038c2ecf20Sopenharmony_ci fimd@11c00000 { 1048c2ecf20Sopenharmony_ci pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; 1058c2ecf20Sopenharmony_ci pinctrl-names = "default"; 1068c2ecf20Sopenharmony_ci status = "okay"; 1078c2ecf20Sopenharmony_ci }; 108