18c2ecf20Sopenharmony_ciDevice-Tree bindings for Samsung Exynos7 SoC display controller (DECON) 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciDECON (Display and Enhancement Controller) is the Display Controller for the 48c2ecf20Sopenharmony_ciExynos7 series of SoCs which transfers the image data from a video memory 58c2ecf20Sopenharmony_cibuffer to an external LCD interface. 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciRequired properties: 88c2ecf20Sopenharmony_ci- compatible: value should be "samsung,exynos7-decon"; 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci- reg: physical base address and length of the DECON registers set. 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci- interrupts: should contain a list of all DECON IP block interrupts in the 138c2ecf20Sopenharmony_ci order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier 148c2ecf20Sopenharmony_ci format depends on the interrupt controller used. 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci- interrupt-names: should contain the interrupt names: "fifo", "vsync", 178c2ecf20Sopenharmony_ci "lcd_sys", in the same order as they were listed in the interrupts 188c2ecf20Sopenharmony_ci property. 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ci- pinctrl-0: pin control group to be used for this controller. 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci- pinctrl-names: must contain a "default" entry. 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ci- clocks: must include clock specifiers corresponding to entries in the 258c2ecf20Sopenharmony_ci clock-names property. 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ci- clock-names: list of clock names sorted in the same order as the clocks 288c2ecf20Sopenharmony_ci property. Must contain "pclk_decon0", "aclk_decon0", 298c2ecf20Sopenharmony_ci "decon0_eclk", "decon0_vclk". 308c2ecf20Sopenharmony_ci- i80-if-timings: timing configuration for lcd i80 interface support. 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ciOptional Properties: 338c2ecf20Sopenharmony_ci- power-domains: a phandle to DECON power domain node. 348c2ecf20Sopenharmony_ci- display-timings: timing settings for DECON, as described in document [1]. 358c2ecf20Sopenharmony_ci Can be used in case timings cannot be provided otherwise 368c2ecf20Sopenharmony_ci or to override timings provided by the panel. 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ci[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt 398c2ecf20Sopenharmony_ci 408c2ecf20Sopenharmony_ciExample: 418c2ecf20Sopenharmony_ci 428c2ecf20Sopenharmony_ciSoC specific DT entry: 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_ci decon@13930000 { 458c2ecf20Sopenharmony_ci compatible = "samsung,exynos7-decon"; 468c2ecf20Sopenharmony_ci interrupt-parent = <&combiner>; 478c2ecf20Sopenharmony_ci reg = <0x13930000 0x1000>; 488c2ecf20Sopenharmony_ci interrupt-names = "lcd_sys", "vsync", "fifo"; 498c2ecf20Sopenharmony_ci interrupts = <0 188 0>, <0 189 0>, <0 190 0>; 508c2ecf20Sopenharmony_ci clocks = <&clock_disp PCLK_DECON_INT>, 518c2ecf20Sopenharmony_ci <&clock_disp ACLK_DECON_INT>, 528c2ecf20Sopenharmony_ci <&clock_disp SCLK_DECON_INT_ECLK>, 538c2ecf20Sopenharmony_ci <&clock_disp SCLK_DECON_INT_EXTCLKPLL>; 548c2ecf20Sopenharmony_ci clock-names = "pclk_decon0", "aclk_decon0", "decon0_eclk", 558c2ecf20Sopenharmony_ci "decon0_vclk"; 568c2ecf20Sopenharmony_ci status = "disabled"; 578c2ecf20Sopenharmony_ci }; 588c2ecf20Sopenharmony_ci 598c2ecf20Sopenharmony_ciBoard specific DT entry: 608c2ecf20Sopenharmony_ci 618c2ecf20Sopenharmony_ci decon@13930000 { 628c2ecf20Sopenharmony_ci pinctrl-0 = <&lcd_clk &pwm1_out>; 638c2ecf20Sopenharmony_ci pinctrl-names = "default"; 648c2ecf20Sopenharmony_ci status = "okay"; 658c2ecf20Sopenharmony_ci }; 66