18c2ecf20Sopenharmony_ciDevice-Tree bindings for Samsung Exynos SoC display controller (DECON) 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciDECON (Display and Enhancement Controller) is the Display Controller for the 48c2ecf20Sopenharmony_ciExynos series of SoCs which transfers the image data from a video memory 58c2ecf20Sopenharmony_cibuffer to an external LCD interface. 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciRequired properties: 88c2ecf20Sopenharmony_ci- compatible: value should be one of: 98c2ecf20Sopenharmony_ci "samsung,exynos5433-decon", "samsung,exynos5433-decon-tv"; 108c2ecf20Sopenharmony_ci- reg: physical base address and length of the DECON registers set. 118c2ecf20Sopenharmony_ci- interrupt-names: should contain the interrupt names depending on mode of work: 128c2ecf20Sopenharmony_ci video mode: "vsync", 138c2ecf20Sopenharmony_ci command mode: "lcd_sys", 148c2ecf20Sopenharmony_ci command mode with software trigger: "lcd_sys", "te". 158c2ecf20Sopenharmony_ci- interrupts or interrupts-extended: list of interrupt specifiers corresponding 168c2ecf20Sopenharmony_ci to names privided in interrupt-names, as described in 178c2ecf20Sopenharmony_ci interrupt-controller/interrupts.txt 188c2ecf20Sopenharmony_ci- clocks: must include clock specifiers corresponding to entries in the 198c2ecf20Sopenharmony_ci clock-names property. 208c2ecf20Sopenharmony_ci- clock-names: list of clock names sorted in the same order as the clocks 218c2ecf20Sopenharmony_ci property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x", 228c2ecf20Sopenharmony_ci "aclk_xiu_decon0x", "pclk_smmu_decon0x", "aclk_smmu_decon1x", 238c2ecf20Sopenharmony_ci "aclk_xiu_decon1x", "pclk_smmu_decon1x", clk_decon_vclk", 248c2ecf20Sopenharmony_ci "sclk_decon_eclk" 258c2ecf20Sopenharmony_ci- ports: contains a port which is connected to mic node. address-cells and 268c2ecf20Sopenharmony_ci size-cells must 1 and 0, respectively. 278c2ecf20Sopenharmony_ci- port: contains an endpoint node which is connected to the endpoint in the mic 288c2ecf20Sopenharmony_ci node. The reg value muset be 0. 298c2ecf20Sopenharmony_ci 308c2ecf20Sopenharmony_ciExample: 318c2ecf20Sopenharmony_ciSoC specific DT entry: 328c2ecf20Sopenharmony_cidecon: decon@13800000 { 338c2ecf20Sopenharmony_ci compatible = "samsung,exynos5433-decon"; 348c2ecf20Sopenharmony_ci reg = <0x13800000 0x2104>; 358c2ecf20Sopenharmony_ci clocks = <&cmu_disp CLK_ACLK_DECON>, <&cmu_disp CLK_ACLK_SMMU_DECON0X>, 368c2ecf20Sopenharmony_ci <&cmu_disp CLK_ACLK_XIU_DECON0X>, 378c2ecf20Sopenharmony_ci <&cmu_disp CLK_PCLK_SMMU_DECON0X>, 388c2ecf20Sopenharmony_ci <&cmu_disp CLK_ACLK_SMMU_DECON1X>, 398c2ecf20Sopenharmony_ci <&cmu_disp CLK_ACLK_XIU_DECON1X>, 408c2ecf20Sopenharmony_ci <&cmu_disp CLK_PCLK_SMMU_DECON1X>, 418c2ecf20Sopenharmony_ci <&cmu_disp CLK_SCLK_DECON_VCLK>, 428c2ecf20Sopenharmony_ci <&cmu_disp CLK_SCLK_DECON_ECLK>; 438c2ecf20Sopenharmony_ci clock-names = "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x", 448c2ecf20Sopenharmony_ci "pclk_smmu_decon0x", "aclk_smmu_decon1x", "aclk_xiu_decon1x", 458c2ecf20Sopenharmony_ci "pclk_smmu_decon1x", "sclk_decon_vclk", "sclk_decon_eclk"; 468c2ecf20Sopenharmony_ci interrupt-names = "vsync", "lcd_sys"; 478c2ecf20Sopenharmony_ci interrupts = <0 202 0>, <0 203 0>; 488c2ecf20Sopenharmony_ci 498c2ecf20Sopenharmony_ci ports { 508c2ecf20Sopenharmony_ci #address-cells = <1>; 518c2ecf20Sopenharmony_ci #size-cells = <0>; 528c2ecf20Sopenharmony_ci 538c2ecf20Sopenharmony_ci port@0 { 548c2ecf20Sopenharmony_ci reg = <0>; 558c2ecf20Sopenharmony_ci decon_to_mic: endpoint { 568c2ecf20Sopenharmony_ci remote-endpoint = <&mic_to_decon>; 578c2ecf20Sopenharmony_ci }; 588c2ecf20Sopenharmony_ci }; 598c2ecf20Sopenharmony_ci }; 608c2ecf20Sopenharmony_ci}; 61