18c2ecf20Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 28c2ecf20Sopenharmony_ci%YAML 1.2 38c2ecf20Sopenharmony_ci--- 48c2ecf20Sopenharmony_ci$id: http://devicetree.org/schemas/display/bridge/thine,thc63lvd1024.yaml# 58c2ecf20Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_cititle: Thine Electronics THC63LVD1024 LVDS Decoder 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_cimaintainers: 108c2ecf20Sopenharmony_ci - Jacopo Mondi <jacopo+renesas@jmondi.org> 118c2ecf20Sopenharmony_ci - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_cidescription: | 148c2ecf20Sopenharmony_ci The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS 158c2ecf20Sopenharmony_ci streams to parallel data outputs. The chip supports single/dual input/output 168c2ecf20Sopenharmony_ci modes, handling up to two LVDS input streams and up to two digital CMOS/TTL 178c2ecf20Sopenharmony_ci outputs. 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ci Single or dual operation mode, output data mapping and DDR output modes are 208c2ecf20Sopenharmony_ci configured through input signals and the chip does not expose any control 218c2ecf20Sopenharmony_ci bus. 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ciproperties: 248c2ecf20Sopenharmony_ci compatible: 258c2ecf20Sopenharmony_ci const: thine,thc63lvd1024 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ci ports: 288c2ecf20Sopenharmony_ci type: object 298c2ecf20Sopenharmony_ci description: | 308c2ecf20Sopenharmony_ci This device has four video ports. Their connections are modeled using the 318c2ecf20Sopenharmony_ci OF graph bindings specified in Documentation/devicetree/bindings/graph.txt. 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci The device can operate in single-link mode or dual-link mode. In 348c2ecf20Sopenharmony_ci single-link mode, all pixels are received on port@0, and port@1 shall not 358c2ecf20Sopenharmony_ci contain any endpoint. In dual-link mode, even-numbered pixels are 368c2ecf20Sopenharmony_ci received on port@0 and odd-numbered pixels on port@1, and both port@0 and 378c2ecf20Sopenharmony_ci port@1 shall contain endpoints. 388c2ecf20Sopenharmony_ci 398c2ecf20Sopenharmony_ci properties: 408c2ecf20Sopenharmony_ci '#address-cells': 418c2ecf20Sopenharmony_ci const: 1 428c2ecf20Sopenharmony_ci 438c2ecf20Sopenharmony_ci '#size-cells': 448c2ecf20Sopenharmony_ci const: 0 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci port@0: 478c2ecf20Sopenharmony_ci type: object 488c2ecf20Sopenharmony_ci description: First LVDS input port 498c2ecf20Sopenharmony_ci 508c2ecf20Sopenharmony_ci port@1: 518c2ecf20Sopenharmony_ci type: object 528c2ecf20Sopenharmony_ci description: Second LVDS input port 538c2ecf20Sopenharmony_ci 548c2ecf20Sopenharmony_ci port@2: 558c2ecf20Sopenharmony_ci type: object 568c2ecf20Sopenharmony_ci description: First digital CMOS/TTL parallel output 578c2ecf20Sopenharmony_ci 588c2ecf20Sopenharmony_ci port@3: 598c2ecf20Sopenharmony_ci type: object 608c2ecf20Sopenharmony_ci description: Second digital CMOS/TTL parallel output 618c2ecf20Sopenharmony_ci 628c2ecf20Sopenharmony_ci required: 638c2ecf20Sopenharmony_ci - port@0 648c2ecf20Sopenharmony_ci - port@2 658c2ecf20Sopenharmony_ci 668c2ecf20Sopenharmony_ci additionalProperties: false 678c2ecf20Sopenharmony_ci 688c2ecf20Sopenharmony_ci oe-gpios: 698c2ecf20Sopenharmony_ci maxItems: 1 708c2ecf20Sopenharmony_ci description: Output enable GPIO signal, pin name "OE", active high. 718c2ecf20Sopenharmony_ci 728c2ecf20Sopenharmony_ci powerdown-gpios: 738c2ecf20Sopenharmony_ci maxItems: 1 748c2ecf20Sopenharmony_ci description: Power down GPIO signal, pin name "/PDWN", active low. 758c2ecf20Sopenharmony_ci 768c2ecf20Sopenharmony_ci vcc-supply: 778c2ecf20Sopenharmony_ci maxItems: 1 788c2ecf20Sopenharmony_ci description: 798c2ecf20Sopenharmony_ci Power supply for the TTL output, TTL CLOCKOUT signal, LVDS input, PLL and 808c2ecf20Sopenharmony_ci digital circuitry. 818c2ecf20Sopenharmony_ci 828c2ecf20Sopenharmony_cirequired: 838c2ecf20Sopenharmony_ci - compatible 848c2ecf20Sopenharmony_ci - ports 858c2ecf20Sopenharmony_ci - vcc-supply 868c2ecf20Sopenharmony_ci 878c2ecf20Sopenharmony_ciadditionalProperties: false 888c2ecf20Sopenharmony_ci 898c2ecf20Sopenharmony_ciexamples: 908c2ecf20Sopenharmony_ci - | 918c2ecf20Sopenharmony_ci #include <dt-bindings/gpio/gpio.h> 928c2ecf20Sopenharmony_ci 938c2ecf20Sopenharmony_ci lvds-decoder { 948c2ecf20Sopenharmony_ci compatible = "thine,thc63lvd1024"; 958c2ecf20Sopenharmony_ci 968c2ecf20Sopenharmony_ci vcc-supply = <®_lvds_vcc>; 978c2ecf20Sopenharmony_ci powerdown-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; 988c2ecf20Sopenharmony_ci 998c2ecf20Sopenharmony_ci ports { 1008c2ecf20Sopenharmony_ci #address-cells = <1>; 1018c2ecf20Sopenharmony_ci #size-cells = <0>; 1028c2ecf20Sopenharmony_ci 1038c2ecf20Sopenharmony_ci port@0 { 1048c2ecf20Sopenharmony_ci reg = <0>; 1058c2ecf20Sopenharmony_ci 1068c2ecf20Sopenharmony_ci lvds_dec_in_0: endpoint { 1078c2ecf20Sopenharmony_ci remote-endpoint = <&lvds_out>; 1088c2ecf20Sopenharmony_ci }; 1098c2ecf20Sopenharmony_ci }; 1108c2ecf20Sopenharmony_ci 1118c2ecf20Sopenharmony_ci port@2 { 1128c2ecf20Sopenharmony_ci reg = <2>; 1138c2ecf20Sopenharmony_ci 1148c2ecf20Sopenharmony_ci lvds_dec_out_2: endpoint { 1158c2ecf20Sopenharmony_ci remote-endpoint = <&adv7511_in>; 1168c2ecf20Sopenharmony_ci }; 1178c2ecf20Sopenharmony_ci }; 1188c2ecf20Sopenharmony_ci }; 1198c2ecf20Sopenharmony_ci }; 1208c2ecf20Sopenharmony_ci 1218c2ecf20Sopenharmony_ci... 122