18c2ecf20Sopenharmony_ciDevice Tree bindings for Armada DRM CRTC driver 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciRequired properties: 48c2ecf20Sopenharmony_ci - compatible: value should be "marvell,dove-lcd". 58c2ecf20Sopenharmony_ci - reg: base address and size of the LCD controller 68c2ecf20Sopenharmony_ci - interrupts: single interrupt number for the LCD controller 78c2ecf20Sopenharmony_ci - port: video output port with endpoints, as described by graph.txt 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ciOptional properties: 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci - clocks: as described by clock-bindings.txt 128c2ecf20Sopenharmony_ci - clock-names: as described by clock-bindings.txt 138c2ecf20Sopenharmony_ci "axiclk" - axi bus clock for pixel clock 148c2ecf20Sopenharmony_ci "plldivider" - pll divider clock for pixel clock 158c2ecf20Sopenharmony_ci "ext_ref_clk0" - external clock 0 for pixel clock 168c2ecf20Sopenharmony_ci "ext_ref_clk1" - external clock 1 for pixel clock 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ciNote: all clocks are optional but at least one must be specified. 198c2ecf20Sopenharmony_ciFurther clocks may be added in the future according to requirements of 208c2ecf20Sopenharmony_cidifferent SoCs. 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ciExample: 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ci lcd0: lcd-controller@820000 { 258c2ecf20Sopenharmony_ci compatible = "marvell,dove-lcd"; 268c2ecf20Sopenharmony_ci reg = <0x820000 0x1000>; 278c2ecf20Sopenharmony_ci interrupts = <47>; 288c2ecf20Sopenharmony_ci clocks = <&si5351 0>; 298c2ecf20Sopenharmony_ci clock-names = "ext_ref_clk_1"; 308c2ecf20Sopenharmony_ci }; 31