18c2ecf20Sopenharmony_ci* ARM PrimeCell Color LCD Controller PL110/PL111 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciSee also Documentation/devicetree/bindings/arm/primecell.yaml 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ciRequired properties: 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ci- compatible: must be one of: 88c2ecf20Sopenharmony_ci "arm,pl110", "arm,primecell" 98c2ecf20Sopenharmony_ci "arm,pl111", "arm,primecell" 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci- reg: base address and size of the control registers block 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci- interrupt-names: either the single entry "combined" representing a 148c2ecf20Sopenharmony_ci combined interrupt output (CLCDINTR), or the four entries 158c2ecf20Sopenharmony_ci "mbe", "vcomp", "lnbu", "fuf" representing the individual 168c2ecf20Sopenharmony_ci CLCDMBEINTR, CLCDVCOMPINTR, CLCDLNBUINTR, CLCDFUFINTR interrupts 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ci- interrupts: contains an interrupt specifier for each entry in 198c2ecf20Sopenharmony_ci interrupt-names 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ci- clock-names: should contain "clcdclk" and "apb_pclk" 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci- clocks: contains phandle and clock specifier pairs for the entries 248c2ecf20Sopenharmony_ci in the clock-names property. See 258c2ecf20Sopenharmony_ci Documentation/devicetree/bindings/clock/clock-bindings.txt 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ciOptional properties: 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ci- memory-region: phandle to a node describing memory (see 308c2ecf20Sopenharmony_ci Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) 318c2ecf20Sopenharmony_ci to be used for the framebuffer; if not present, the framebuffer 328c2ecf20Sopenharmony_ci may be located anywhere in the memory 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_ci- max-memory-bandwidth: maximum bandwidth in bytes per second that the 358c2ecf20Sopenharmony_ci cell's memory interface can handle; if not present, the memory 368c2ecf20Sopenharmony_ci interface is fast enough to handle all possible video modes 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ciRequired sub-nodes: 398c2ecf20Sopenharmony_ci 408c2ecf20Sopenharmony_ci- port: describes LCD panel signals, following the common binding 418c2ecf20Sopenharmony_ci for video transmitter interfaces; see 428c2ecf20Sopenharmony_ci Documentation/devicetree/bindings/media/video-interfaces.txt 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_ciDeprecated properties: 458c2ecf20Sopenharmony_ci The port's endbpoint subnode had this, now deprecated property 468c2ecf20Sopenharmony_ci in the past. Drivers should be able to survive without it: 478c2ecf20Sopenharmony_ci 488c2ecf20Sopenharmony_ci - arm,pl11x,tft-r0g0b0-pads: an array of three 32-bit values, 498c2ecf20Sopenharmony_ci defining the way CLD pads are wired up; first value 508c2ecf20Sopenharmony_ci contains index of the "CLD" external pin (pad) used 518c2ecf20Sopenharmony_ci as R0 (first bit of the red component), second value 528c2ecf20Sopenharmony_ci index of the pad used as G0, third value index of the 538c2ecf20Sopenharmony_ci pad used as B0, see also "LCD panel signal multiplexing 548c2ecf20Sopenharmony_ci details" paragraphs in the PL110/PL111 Technical 558c2ecf20Sopenharmony_ci Reference Manuals; this implicitly defines available 568c2ecf20Sopenharmony_ci color modes, for example: 578c2ecf20Sopenharmony_ci - PL111 TFT 4:4:4 panel: 588c2ecf20Sopenharmony_ci arm,pl11x,tft-r0g0b0-pads = <4 15 20>; 598c2ecf20Sopenharmony_ci - PL110 TFT (1:)5:5:5 panel: 608c2ecf20Sopenharmony_ci arm,pl11x,tft-r0g0b0-pads = <1 7 13>; 618c2ecf20Sopenharmony_ci - PL111 TFT (1:)5:5:5 panel: 628c2ecf20Sopenharmony_ci arm,pl11x,tft-r0g0b0-pads = <3 11 19>; 638c2ecf20Sopenharmony_ci - PL111 TFT 5:6:5 panel: 648c2ecf20Sopenharmony_ci arm,pl11x,tft-r0g0b0-pads = <3 10 19>; 658c2ecf20Sopenharmony_ci - PL110 and PL111 TFT 8:8:8 panel: 668c2ecf20Sopenharmony_ci arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 678c2ecf20Sopenharmony_ci - PL110 and PL111 TFT 8:8:8 panel, R & B components swapped: 688c2ecf20Sopenharmony_ci arm,pl11x,tft-r0g0b0-pads = <16 8 0>; 698c2ecf20Sopenharmony_ci 708c2ecf20Sopenharmony_ci 718c2ecf20Sopenharmony_ciExample: 728c2ecf20Sopenharmony_ci 738c2ecf20Sopenharmony_ci clcd@10020000 { 748c2ecf20Sopenharmony_ci compatible = "arm,pl111", "arm,primecell"; 758c2ecf20Sopenharmony_ci reg = <0x10020000 0x1000>; 768c2ecf20Sopenharmony_ci interrupt-names = "combined"; 778c2ecf20Sopenharmony_ci interrupts = <0 44 4>; 788c2ecf20Sopenharmony_ci clocks = <&oscclk1>, <&oscclk2>; 798c2ecf20Sopenharmony_ci clock-names = "clcdclk", "apb_pclk"; 808c2ecf20Sopenharmony_ci max-memory-bandwidth = <94371840>; /* Bps, 1024x768@60 16bpp */ 818c2ecf20Sopenharmony_ci 828c2ecf20Sopenharmony_ci port { 838c2ecf20Sopenharmony_ci clcd_pads: endpoint { 848c2ecf20Sopenharmony_ci remote-endpoint = <&clcd_panel>; 858c2ecf20Sopenharmony_ci }; 868c2ecf20Sopenharmony_ci }; 878c2ecf20Sopenharmony_ci 888c2ecf20Sopenharmony_ci }; 898c2ecf20Sopenharmony_ci 908c2ecf20Sopenharmony_ci panel { 918c2ecf20Sopenharmony_ci compatible = "panel-dpi"; 928c2ecf20Sopenharmony_ci 938c2ecf20Sopenharmony_ci port { 948c2ecf20Sopenharmony_ci clcd_panel: endpoint { 958c2ecf20Sopenharmony_ci remote-endpoint = <&clcd_pads>; 968c2ecf20Sopenharmony_ci }; 978c2ecf20Sopenharmony_ci }; 988c2ecf20Sopenharmony_ci 998c2ecf20Sopenharmony_ci panel-timing { 1008c2ecf20Sopenharmony_ci clock-frequency = <25175000>; 1018c2ecf20Sopenharmony_ci hactive = <640>; 1028c2ecf20Sopenharmony_ci hback-porch = <40>; 1038c2ecf20Sopenharmony_ci hfront-porch = <24>; 1048c2ecf20Sopenharmony_ci hsync-len = <96>; 1058c2ecf20Sopenharmony_ci vactive = <480>; 1068c2ecf20Sopenharmony_ci vback-porch = <32>; 1078c2ecf20Sopenharmony_ci vfront-porch = <11>; 1088c2ecf20Sopenharmony_ci vsync-len = <2>; 1098c2ecf20Sopenharmony_ci }; 1108c2ecf20Sopenharmony_ci }; 111