18c2ecf20Sopenharmony_ciARM HDLCD
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciThis is a display controller found on several development platforms produced
48c2ecf20Sopenharmony_ciby ARM Ltd and in more modern of its' Fast Models. The HDLCD is an RGB
58c2ecf20Sopenharmony_cistreamer that reads the data from a framebuffer and sends it to a single
68c2ecf20Sopenharmony_cidigital encoder (DVI or HDMI).
78c2ecf20Sopenharmony_ci
88c2ecf20Sopenharmony_ciRequired properties:
98c2ecf20Sopenharmony_ci  - compatible: "arm,hdlcd"
108c2ecf20Sopenharmony_ci  - reg: Physical base address and length of the controller's registers.
118c2ecf20Sopenharmony_ci  - interrupts: One interrupt used by the display controller to notify the
128c2ecf20Sopenharmony_ci    interrupt controller when any of the interrupt sources programmed in
138c2ecf20Sopenharmony_ci    the interrupt mask register have activated.
148c2ecf20Sopenharmony_ci  - clocks: A list of phandle + clock-specifier pairs, one for each
158c2ecf20Sopenharmony_ci    entry in 'clock-names'.
168c2ecf20Sopenharmony_ci  - clock-names: A list of clock names. For HDLCD it should contain:
178c2ecf20Sopenharmony_ci      - "pxlclk" for the clock feeding the output PLL of the controller.
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ciRequired sub-nodes:
208c2ecf20Sopenharmony_ci  - port: The HDLCD connection to an encoder chip. The connection is modeled
218c2ecf20Sopenharmony_ci    using the OF graph bindings specified in
228c2ecf20Sopenharmony_ci    Documentation/devicetree/bindings/graph.txt.
238c2ecf20Sopenharmony_ci
248c2ecf20Sopenharmony_ciOptional properties:
258c2ecf20Sopenharmony_ci  - memory-region: phandle to a node describing memory (see
268c2ecf20Sopenharmony_ci    Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) to be
278c2ecf20Sopenharmony_ci    used for the framebuffer; if not present, the framebuffer may be located
288c2ecf20Sopenharmony_ci    anywhere in memory.
298c2ecf20Sopenharmony_ci
308c2ecf20Sopenharmony_ci
318c2ecf20Sopenharmony_ciExample:
328c2ecf20Sopenharmony_ci
338c2ecf20Sopenharmony_ci/ {
348c2ecf20Sopenharmony_ci	...
358c2ecf20Sopenharmony_ci
368c2ecf20Sopenharmony_ci	hdlcd@2b000000 {
378c2ecf20Sopenharmony_ci		compatible = "arm,hdlcd";
388c2ecf20Sopenharmony_ci		reg = <0 0x2b000000 0 0x1000>;
398c2ecf20Sopenharmony_ci		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
408c2ecf20Sopenharmony_ci		clocks = <&oscclk5>;
418c2ecf20Sopenharmony_ci		clock-names = "pxlclk";
428c2ecf20Sopenharmony_ci		port {
438c2ecf20Sopenharmony_ci			hdlcd_output: endpoint@0 {
448c2ecf20Sopenharmony_ci				remote-endpoint = <&hdmi_enc_input>;
458c2ecf20Sopenharmony_ci			};
468c2ecf20Sopenharmony_ci		};
478c2ecf20Sopenharmony_ci	};
488c2ecf20Sopenharmony_ci
498c2ecf20Sopenharmony_ci	/* HDMI encoder on I2C bus */
508c2ecf20Sopenharmony_ci	i2c@7ffa0000 {
518c2ecf20Sopenharmony_ci		....
528c2ecf20Sopenharmony_ci		hdmi-transmitter@70 {
538c2ecf20Sopenharmony_ci			compatible = ".....";
548c2ecf20Sopenharmony_ci			reg = <0x70>;
558c2ecf20Sopenharmony_ci			port@0 {
568c2ecf20Sopenharmony_ci				hdmi_enc_input: endpoint {
578c2ecf20Sopenharmony_ci					remote-endpoint = <&hdlcd_output>;
588c2ecf20Sopenharmony_ci				};
598c2ecf20Sopenharmony_ci
608c2ecf20Sopenharmony_ci				hdmi_enc_output: endpoint {
618c2ecf20Sopenharmony_ci					remote-endpoint = <&hdmi_1_port>;
628c2ecf20Sopenharmony_ci				};
638c2ecf20Sopenharmony_ci			};
648c2ecf20Sopenharmony_ci		};
658c2ecf20Sopenharmony_ci
668c2ecf20Sopenharmony_ci	};
678c2ecf20Sopenharmony_ci
688c2ecf20Sopenharmony_ci	hdmi1: connector@1 {
698c2ecf20Sopenharmony_ci		compatible = "hdmi-connector";
708c2ecf20Sopenharmony_ci		type = "a";
718c2ecf20Sopenharmony_ci		port {
728c2ecf20Sopenharmony_ci			hdmi_1_port: endpoint {
738c2ecf20Sopenharmony_ci				remote-endpoint = <&hdmi_enc_output>;
748c2ecf20Sopenharmony_ci			};
758c2ecf20Sopenharmony_ci		};
768c2ecf20Sopenharmony_ci	};
778c2ecf20Sopenharmony_ci
788c2ecf20Sopenharmony_ci	...
798c2ecf20Sopenharmony_ci};
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