18c2ecf20Sopenharmony_ciThe Broadcom Secure Processing Unit (SPU) hardware supports symmetric 28c2ecf20Sopenharmony_cicryptographic offload for Broadcom SoCs. A SoC may have multiple SPU hardware 38c2ecf20Sopenharmony_ciblocks. 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ciRequired properties: 68c2ecf20Sopenharmony_ci- compatible: Should be one of the following: 78c2ecf20Sopenharmony_ci brcm,spum-crypto - for devices with SPU-M hardware 88c2ecf20Sopenharmony_ci brcm,spu2-crypto - for devices with SPU2 hardware 98c2ecf20Sopenharmony_ci brcm,spu2-v2-crypto - for devices with enhanced SPU2 hardware features like SHA3 108c2ecf20Sopenharmony_ci and Rabin Fingerprint support 118c2ecf20Sopenharmony_ci brcm,spum-nsp-crypto - for the Northstar Plus variant of the SPU-M hardware 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci- reg: Should contain SPU registers location and length. 148c2ecf20Sopenharmony_ci- mboxes: The mailbox channel to be used to communicate with the SPU. 158c2ecf20Sopenharmony_ci Mailbox channels correspond to DMA rings on the device. 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ciExample: 188c2ecf20Sopenharmony_ci crypto@612d0000 { 198c2ecf20Sopenharmony_ci compatible = "brcm,spum-crypto"; 208c2ecf20Sopenharmony_ci reg = <0 0x612d0000 0 0x900>; 218c2ecf20Sopenharmony_ci mboxes = <&pdc0 0>; 228c2ecf20Sopenharmony_ci }; 23