18c2ecf20Sopenharmony_ciBinding for NVIDIA Tegra20 CPUFreq 28c2ecf20Sopenharmony_ci================================== 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ciRequired properties: 58c2ecf20Sopenharmony_ci- clocks: Must contain an entry for the CPU clock. 68c2ecf20Sopenharmony_ci See ../clocks/clock-bindings.txt for details. 78c2ecf20Sopenharmony_ci- operating-points-v2: See ../bindings/opp/opp.txt for details. 88c2ecf20Sopenharmony_ci- #cooling-cells: Should be 2. See ../thermal/thermal-cooling-devices.yaml for details. 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ciFor each opp entry in 'operating-points-v2' table: 118c2ecf20Sopenharmony_ci- opp-supported-hw: Two bitfields indicating: 128c2ecf20Sopenharmony_ci On Tegra20: 138c2ecf20Sopenharmony_ci 1. CPU process ID mask 148c2ecf20Sopenharmony_ci 2. SoC speedo ID mask 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci On Tegra30: 178c2ecf20Sopenharmony_ci 1. CPU process ID mask 188c2ecf20Sopenharmony_ci 2. CPU speedo ID mask 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ci A bitwise AND is performed against these values and if any bit 218c2ecf20Sopenharmony_ci matches, the OPP gets enabled. 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci- opp-microvolt: CPU voltage triplet. 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ciOptional properties: 268c2ecf20Sopenharmony_ci- cpu-supply: Phandle to the CPU power supply. 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_ciExample: 298c2ecf20Sopenharmony_ci regulators { 308c2ecf20Sopenharmony_ci cpu_reg: regulator0 { 318c2ecf20Sopenharmony_ci regulator-name = "vdd_cpu"; 328c2ecf20Sopenharmony_ci }; 338c2ecf20Sopenharmony_ci }; 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_ci cpu0_opp_table: opp_table0 { 368c2ecf20Sopenharmony_ci compatible = "operating-points-v2"; 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ci opp@456000000 { 398c2ecf20Sopenharmony_ci clock-latency-ns = <125000>; 408c2ecf20Sopenharmony_ci opp-microvolt = <825000 825000 1125000>; 418c2ecf20Sopenharmony_ci opp-supported-hw = <0x03 0x0001>; 428c2ecf20Sopenharmony_ci opp-hz = /bits/ 64 <456000000>; 438c2ecf20Sopenharmony_ci }; 448c2ecf20Sopenharmony_ci 458c2ecf20Sopenharmony_ci ... 468c2ecf20Sopenharmony_ci }; 478c2ecf20Sopenharmony_ci 488c2ecf20Sopenharmony_ci cpus { 498c2ecf20Sopenharmony_ci cpu@0 { 508c2ecf20Sopenharmony_ci compatible = "arm,cortex-a9"; 518c2ecf20Sopenharmony_ci clocks = <&tegra_car TEGRA20_CLK_CCLK>; 528c2ecf20Sopenharmony_ci operating-points-v2 = <&cpu0_opp_table>; 538c2ecf20Sopenharmony_ci cpu-supply = <&cpu_reg>; 548c2ecf20Sopenharmony_ci #cooling-cells = <2>; 558c2ecf20Sopenharmony_ci }; 568c2ecf20Sopenharmony_ci }; 57