18c2ecf20Sopenharmony_ciSPEAr cpufreq driver 28c2ecf20Sopenharmony_ci------------------- 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ciSPEAr SoC cpufreq driver for CPU frequency scaling. 58c2ecf20Sopenharmony_ciIt supports both uniprocessor (UP) and symmetric multiprocessor (SMP) systems 68c2ecf20Sopenharmony_ciwhich share clock across all CPUs. 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ciRequired properties: 98c2ecf20Sopenharmony_ci- cpufreq_tbl: Table of frequencies CPU could be transitioned into, in the 108c2ecf20Sopenharmony_ci increasing order. 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ciOptional properties: 138c2ecf20Sopenharmony_ci- clock-latency: Specify the possible maximum transition latency for clock, in 148c2ecf20Sopenharmony_ci unit of nanoseconds. 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ciBoth required and optional properties listed above must be defined under node 178c2ecf20Sopenharmony_ci/cpus/cpu@0. 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ciExamples: 208c2ecf20Sopenharmony_ci-------- 218c2ecf20Sopenharmony_cicpus { 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci <...> 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ci cpu@0 { 268c2ecf20Sopenharmony_ci compatible = "arm,cortex-a9"; 278c2ecf20Sopenharmony_ci reg = <0>; 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ci <...> 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ci cpufreq_tbl = < 166000 328c2ecf20Sopenharmony_ci 200000 338c2ecf20Sopenharmony_ci 250000 348c2ecf20Sopenharmony_ci 300000 358c2ecf20Sopenharmony_ci 400000 368c2ecf20Sopenharmony_ci 500000 378c2ecf20Sopenharmony_ci 600000 >; 388c2ecf20Sopenharmony_ci }; 398c2ecf20Sopenharmony_ci 408c2ecf20Sopenharmony_ci <...> 418c2ecf20Sopenharmony_ci 428c2ecf20Sopenharmony_ci}; 43