18c2ecf20Sopenharmony_ciDevice Tree Clock bindings for ZTE zx296718
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciThis binding uses the common clock binding[1].
48c2ecf20Sopenharmony_ci
58c2ecf20Sopenharmony_ci[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_ciRequired properties:
88c2ecf20Sopenharmony_ci- compatible : shall be one of the following:
98c2ecf20Sopenharmony_ci	"zte,zx296718-topcrm":
108c2ecf20Sopenharmony_ci		zx296718 top clock selection, divider and gating
118c2ecf20Sopenharmony_ci
128c2ecf20Sopenharmony_ci	"zte,zx296718-lsp0crm" and
138c2ecf20Sopenharmony_ci	"zte,zx296718-lsp1crm":
148c2ecf20Sopenharmony_ci		zx296718 device level clock selection and gating
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_ci	"zte,zx296718-audiocrm":
178c2ecf20Sopenharmony_ci		zx296718 audio clock selection, divider and gating
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ci- reg: Address and length of the register set
208c2ecf20Sopenharmony_ci
218c2ecf20Sopenharmony_ciThe clock consumer should specify the desired clock by having the clock
228c2ecf20Sopenharmony_ciID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296718-clock.h
238c2ecf20Sopenharmony_cifor the full list of zx296718 clock IDs.
248c2ecf20Sopenharmony_ci
258c2ecf20Sopenharmony_ci
268c2ecf20Sopenharmony_citopclk: topcrm@1461000 {
278c2ecf20Sopenharmony_ci        compatible = "zte,zx296718-topcrm-clk";
288c2ecf20Sopenharmony_ci        reg = <0x01461000 0x1000>;
298c2ecf20Sopenharmony_ci        #clock-cells = <1>;
308c2ecf20Sopenharmony_ci};
318c2ecf20Sopenharmony_ci
328c2ecf20Sopenharmony_ciusbphy0:usb-phy0 {
338c2ecf20Sopenharmony_ci	compatible = "zte,zx296718-usb-phy";
348c2ecf20Sopenharmony_ci	#phy-cells = <0>;
358c2ecf20Sopenharmony_ci	clocks = <&topclk USB20_PHY_CLK>;
368c2ecf20Sopenharmony_ci	clock-names = "phyclk";
378c2ecf20Sopenharmony_ci};
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