18c2ecf20Sopenharmony_ciDevice Tree Clock bindings for ZTE zx296702 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThis binding uses the common clock binding[1]. 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ci[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciRequired properties: 88c2ecf20Sopenharmony_ci- compatible : shall be one of the following: 98c2ecf20Sopenharmony_ci "zte,zx296702-topcrm-clk": 108c2ecf20Sopenharmony_ci zx296702 top clock selection, divider and gating 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci "zte,zx296702-lsp0crpm-clk" and 138c2ecf20Sopenharmony_ci "zte,zx296702-lsp1crpm-clk": 148c2ecf20Sopenharmony_ci zx296702 device level clock selection and gating 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci- reg: Address and length of the register set 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ciThe clock consumer should specify the desired clock by having the clock 198c2ecf20Sopenharmony_ciID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296702-clock.h 208c2ecf20Sopenharmony_cifor the full list of zx296702 clock IDs. 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_citopclk: topcrm@09800000 { 248c2ecf20Sopenharmony_ci compatible = "zte,zx296702-topcrm-clk"; 258c2ecf20Sopenharmony_ci reg = <0x09800000 0x1000>; 268c2ecf20Sopenharmony_ci #clock-cells = <1>; 278c2ecf20Sopenharmony_ci}; 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ciuart0: serial@09405000 { 308c2ecf20Sopenharmony_ci compatible = "zte,zx296702-uart"; 318c2ecf20Sopenharmony_ci reg = <0x09405000 0x1000>; 328c2ecf20Sopenharmony_ci interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 338c2ecf20Sopenharmony_ci clocks = <&lsp1clk ZX296702_UART0_PCLK>; 348c2ecf20Sopenharmony_ci}; 35