18c2ecf20Sopenharmony_ciClock bindings for ST-Ericsson Ux500 clocks
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciRequired properties :
48c2ecf20Sopenharmony_ci- compatible : shall contain only one of the following:
58c2ecf20Sopenharmony_ci  "stericsson,u8500-clks"
68c2ecf20Sopenharmony_ci  "stericsson,u8540-clks"
78c2ecf20Sopenharmony_ci  "stericsson,u9540-clks"
88c2ecf20Sopenharmony_ci- reg : shall contain base register location and length for
98c2ecf20Sopenharmony_ci  CLKRST1, 2, 3, 5, and 6 in an array. Note the absence of
108c2ecf20Sopenharmony_ci  CLKRST4, which does not exist.
118c2ecf20Sopenharmony_ci
128c2ecf20Sopenharmony_ciRequired subnodes:
138c2ecf20Sopenharmony_ci- prcmu-clock: a subnode with one clock cell for PRCMU (power,
148c2ecf20Sopenharmony_ci  reset, control unit) clocks. The cell indicates which PRCMU
158c2ecf20Sopenharmony_ci  clock in the prcmu-clock node the consumer wants to use.
168c2ecf20Sopenharmony_ci- prcc-periph-clock: a subnode with two clock cells for
178c2ecf20Sopenharmony_ci  PRCC (programmable reset- and clock controller) peripheral clocks.
188c2ecf20Sopenharmony_ci  The first cell indicates which PRCC block the consumer
198c2ecf20Sopenharmony_ci  wants to use, possible values are 1, 2, 3, 5, 6. The second
208c2ecf20Sopenharmony_ci  cell indicates which clock inside the PRCC block it wants,
218c2ecf20Sopenharmony_ci  possible values are 0 thru 31.
228c2ecf20Sopenharmony_ci- prcc-kernel-clock: a subnode with two clock cells for
238c2ecf20Sopenharmony_ci  PRCC (programmable reset- and clock controller) kernel clocks
248c2ecf20Sopenharmony_ci  The first cell indicates which PRCC block the consumer
258c2ecf20Sopenharmony_ci  wants to use, possible values are 1, 2, 3, 5, 6. The second
268c2ecf20Sopenharmony_ci  cell indicates which clock inside the PRCC block it wants,
278c2ecf20Sopenharmony_ci  possible values are 0 thru 31.
288c2ecf20Sopenharmony_ci- rtc32k-clock: a subnode with zero clock cells for the 32kHz
298c2ecf20Sopenharmony_ci  RTC clock.
308c2ecf20Sopenharmony_ci- smp-twd-clock: a subnode for the ARM SMP Timer Watchdog cluster
318c2ecf20Sopenharmony_ci  with zero clock cells.
328c2ecf20Sopenharmony_ci
338c2ecf20Sopenharmony_ciExample:
348c2ecf20Sopenharmony_ci
358c2ecf20Sopenharmony_ciclocks {
368c2ecf20Sopenharmony_ci	compatible = "stericsson,u8500-clks";
378c2ecf20Sopenharmony_ci	/*
388c2ecf20Sopenharmony_ci	 * Registers for the CLKRST block on peripheral
398c2ecf20Sopenharmony_ci	 * groups 1, 2, 3, 5, 6,
408c2ecf20Sopenharmony_ci	 */
418c2ecf20Sopenharmony_ci	reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
428c2ecf20Sopenharmony_ci	    <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
438c2ecf20Sopenharmony_ci	    <0xa03cf000 0x1000>;
448c2ecf20Sopenharmony_ci
458c2ecf20Sopenharmony_ci	prcmu_clk: prcmu-clock {
468c2ecf20Sopenharmony_ci		#clock-cells = <1>;
478c2ecf20Sopenharmony_ci	};
488c2ecf20Sopenharmony_ci
498c2ecf20Sopenharmony_ci	prcc_pclk: prcc-periph-clock {
508c2ecf20Sopenharmony_ci		#clock-cells = <2>;
518c2ecf20Sopenharmony_ci	};
528c2ecf20Sopenharmony_ci
538c2ecf20Sopenharmony_ci	prcc_kclk: prcc-kernel-clock {
548c2ecf20Sopenharmony_ci		#clock-cells = <2>;
558c2ecf20Sopenharmony_ci	};
568c2ecf20Sopenharmony_ci
578c2ecf20Sopenharmony_ci	rtc_clk: rtc32k-clock {
588c2ecf20Sopenharmony_ci		#clock-cells = <0>;
598c2ecf20Sopenharmony_ci	};
608c2ecf20Sopenharmony_ci
618c2ecf20Sopenharmony_ci	smp_twd_clk: smp-twd-clock {
628c2ecf20Sopenharmony_ci		#clock-cells = <0>;
638c2ecf20Sopenharmony_ci	};
648c2ecf20Sopenharmony_ci};
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