18c2ecf20Sopenharmony_ci* Sigma Designs Tango4 Clock Generator
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38c2ecf20Sopenharmony_ciThe Tango4 clock generator outputs cpu_clk and sys_clk (the latter is used
48c2ecf20Sopenharmony_cifor RAM and various peripheral devices). The clock binding described here
58c2ecf20Sopenharmony_ciis applicable to all Tango4 SoCs.
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78c2ecf20Sopenharmony_ciRequired Properties:
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98c2ecf20Sopenharmony_ci- compatible: should be "sigma,tango4-clkgen".
108c2ecf20Sopenharmony_ci- reg: physical base address of the device and length of memory mapped region.
118c2ecf20Sopenharmony_ci- clocks: phandle of the input clock (crystal oscillator).
128c2ecf20Sopenharmony_ci- clock-output-names: should be "cpuclk" and "sysclk".
138c2ecf20Sopenharmony_ci- #clock-cells: should be set to 1.
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158c2ecf20Sopenharmony_ciExample:
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178c2ecf20Sopenharmony_ci	clkgen: clkgen@10000 {
188c2ecf20Sopenharmony_ci		compatible = "sigma,tango4-clkgen";
198c2ecf20Sopenharmony_ci		reg = <0x10000 0x40>;
208c2ecf20Sopenharmony_ci		clocks = <&xtal>;
218c2ecf20Sopenharmony_ci		clock-output-names = "cpuclk", "sysclk";
228c2ecf20Sopenharmony_ci		#clock-cells = <1>;
238c2ecf20Sopenharmony_ci	};
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