18c2ecf20Sopenharmony_ci* Sigma Designs Tango4 Clock Generator 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThe Tango4 clock generator outputs cpu_clk and sys_clk (the latter is used 48c2ecf20Sopenharmony_cifor RAM and various peripheral devices). The clock binding described here 58c2ecf20Sopenharmony_ciis applicable to all Tango4 SoCs. 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciRequired Properties: 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci- compatible: should be "sigma,tango4-clkgen". 108c2ecf20Sopenharmony_ci- reg: physical base address of the device and length of memory mapped region. 118c2ecf20Sopenharmony_ci- clocks: phandle of the input clock (crystal oscillator). 128c2ecf20Sopenharmony_ci- clock-output-names: should be "cpuclk" and "sysclk". 138c2ecf20Sopenharmony_ci- #clock-cells: should be set to 1. 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ciExample: 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci clkgen: clkgen@10000 { 188c2ecf20Sopenharmony_ci compatible = "sigma,tango4-clkgen"; 198c2ecf20Sopenharmony_ci reg = <0x10000 0x40>; 208c2ecf20Sopenharmony_ci clocks = <&xtal>; 218c2ecf20Sopenharmony_ci clock-output-names = "cpuclk", "sysclk"; 228c2ecf20Sopenharmony_ci #clock-cells = <1>; 238c2ecf20Sopenharmony_ci }; 24