18c2ecf20Sopenharmony_ciBinding for a ST pll clock driver.
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciThis binding uses the common clock binding[1].
48c2ecf20Sopenharmony_ciBase address is located to the parent node. See clock binding[2]
58c2ecf20Sopenharmony_ci
68c2ecf20Sopenharmony_ci[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
78c2ecf20Sopenharmony_ci[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
88c2ecf20Sopenharmony_ci
98c2ecf20Sopenharmony_ciRequired properties:
108c2ecf20Sopenharmony_ci
118c2ecf20Sopenharmony_ci- compatible : shall be:
128c2ecf20Sopenharmony_ci	"st,clkgen-pll0"
138c2ecf20Sopenharmony_ci	"st,clkgen-pll1"
148c2ecf20Sopenharmony_ci	"st,stih407-clkgen-plla9"
158c2ecf20Sopenharmony_ci	"st,stih418-clkgen-plla9"
168c2ecf20Sopenharmony_ci
178c2ecf20Sopenharmony_ci- #clock-cells : From common clock binding; shall be set to 1.
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ci- clocks : From common clock binding
208c2ecf20Sopenharmony_ci
218c2ecf20Sopenharmony_ci- clock-output-names : From common clock binding.
228c2ecf20Sopenharmony_ci
238c2ecf20Sopenharmony_ciExample:
248c2ecf20Sopenharmony_ci
258c2ecf20Sopenharmony_ci	clockgen-a9@92b0000 {
268c2ecf20Sopenharmony_ci		compatible = "st,clkgen-c32";
278c2ecf20Sopenharmony_ci		reg = <0x92b0000 0xffff>;
288c2ecf20Sopenharmony_ci
298c2ecf20Sopenharmony_ci		clockgen_a9_pll: clockgen-a9-pll {
308c2ecf20Sopenharmony_ci			#clock-cells = <1>;
318c2ecf20Sopenharmony_ci			compatible = "st,stih407-clkgen-plla9";
328c2ecf20Sopenharmony_ci
338c2ecf20Sopenharmony_ci			clocks = <&clk_sysin>;
348c2ecf20Sopenharmony_ci
358c2ecf20Sopenharmony_ci			clock-output-names = "clockgen-a9-pll-odf";
368c2ecf20Sopenharmony_ci		};
378c2ecf20Sopenharmony_ci	};
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