18c2ecf20Sopenharmony_ciBinding for a ST multiplexed clock driver. 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThis binding supports only simple indexed multiplexers, it does not 48c2ecf20Sopenharmony_cisupport table based parent index to hardware value translations. 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ciThis binding uses the common clock binding[1]. 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ciRequired properties: 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci- compatible : shall be: 138c2ecf20Sopenharmony_ci "st,stih407-clkgen-a9-mux" 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci- #clock-cells : from common clock binding; shall be set to 0. 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci- reg : A Base address and length of the register set. 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ci- clocks : from common clock binding 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ciExample: 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci clk_m_a9: clk-m-a9@92b0000 { 248c2ecf20Sopenharmony_ci #clock-cells = <0>; 258c2ecf20Sopenharmony_ci compatible = "st,stih407-clkgen-a9-mux"; 268c2ecf20Sopenharmony_ci reg = <0x92b0000 0x10000>; 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_ci clocks = <&clockgen_a9_pll 0>, 298c2ecf20Sopenharmony_ci <&clockgen_a9_pll 0>, 308c2ecf20Sopenharmony_ci <&clk_s_c0_flexgen 13>, 318c2ecf20Sopenharmony_ci <&clk_m_a9_ext2f_div2>; 328c2ecf20Sopenharmony_ci }; 33